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Anton Balbekov
Anton Balbekov
Engineer, NIISI
Verified email at cs.niisi.ras.ru
Title
Cited by
Cited by
Year
Circuit-level layout-aware modeling of single-event effects in 65-nm CMOS ICs
AO Balbekov, MS Gorbunov, GI Zebrev
IEEE Transactions on Nuclear Science 65 (8), 1914-1919, 2018
192018
DICE-based Muller C-elements for soft error tolerant asynchronous ICs
IA Danilov, MS Gorbunov, AI Shnaider, AO Balbekov, YB Rogatkin, ...
2016 16th European Conference on Radiation and Its Effects on Components and …, 2016
192016
On board electronic devices safety provided by DICE-based Muller C-elements
IA Danilov, MS Gorbunov, AI Shnaider, AO Balbekov, YB Rogatkin, ...
Acta Astronautica 150, 28-32, 2018
172018
Standard verification flow compatible layout-aware fault injection technique for single event effects tolerant ASIC design
IA Danilov, AIS Khazanova, AO Balbekov, MS Gorbunov
2019 19th European Conference on Radiation and Its Effects on Components and …, 2019
42019
Comparative Analysis of Layout-Aware Fault Injection on TMR-based DMA Controllers
P Chernyakov, A Skorobogatov, A Zvyagin, E Emin, I Danilov, A Balbekov, ...
2019 IEEE 31st International Conference on Microelectronics (MIEL), 289-292, 2019
42019
Estimation technique for SET-tolerance of combinational ICs
A Balbekov, M Gorbunov
International Conference on Micro-and Nano-Electronics 2014 9440, 375-381, 2014
42014
Design-stage hardening of 65-nm cmos standard cells against multiple events
AO Balbekov, MS Gorbunov, AM Galimov
IEEE Transactions on Nuclear Science 68 (8), 1712-1718, 2021
22021
Layout-aware soft error rate estimation technique for integrated circuits under the environment with energetic charged particles
AO Balbekov, MS Gorbunov, SG Bobkov
Journal of Physics: Conference Series 798 (1), 012209, 2017
22017
Layout-aware simulation of soft errors in sub-100 nm integrated circuits
A Balbekov, M Gorbunov, S Bobkov
International Conference on Micro-and Nano-Electronics 2016 10224, 305-310, 2016
22016
SiGe BiCMOS Voltage-Controlled Oscillator and Mixer IP-blocks for the Next-Generation Communication Transceivers
IA Selishchev, DI Sotskov, AG Kuznetsov, NA Usachev, VV Elesin, ...
2021 IEEE 32nd International Conference on Microelectronics (MIEL), 239-242, 2021
12021
SPICE-level layout-aware single event effects simulation of majority voters
AO Balbekov, MS Gorbunov, GI Zebrev
2017 IEEE 30th International Conference on Microelectronics (MIEL), 333-336, 2017
12017
Application of the layout-aware single event simulations to a design of 65 nm memory units
AO Balbekov
2018 Moscow Workshop on Electronic and Networking Technologies (MWENT), 1-4, 2018
2018
Development of fault-tolerant triggers on 65 nm CMOS technology; Razrabotka sboeustojchivykh triggerov na 65 nm KMOP tekhnologii
AO Balbekov, VE Shunkov, PS Dolotov
2013
Development of fault-tolerant triggers on 65 nm CMOS technology
AO Balbekov, VE Shunkov, PS Dolotov
Scientific session of NRNU MEPHI-2013. Abstracts. In three volumes. Volume 1 …, 2013
2013
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Articles 1–14