| Method for creating self-aligned transistor contacts MA Zaleski, ACH Wei, JE Stephens, TG Neogi, G Bouche US Patent 9,236,437, 2016 | 34 | 2016 |
| Innovations in special constructs for standard cell libraries in sub 28nm technologies M Rashed, N Jain, J Kim, M Tarabbia, I Rahim, S Ahmed, J Kim, I Lin, ... 2013 IEEE International Electron Devices Meeting, 9.7. 1-9.7. 4, 2013 | 30 | 2013 |
| Method for creating self-aligned compact contacts in an IC device meeting fabrication spacing constraints G Bouche, A Wei, Y Woo US Patent 9,406,775, 2016 | 20 | 2016 |
| Phase transitions in K2Cr2O7 and structural redeterminations of phase II TJR Weakley, ER Ylvisaker, RJ Yager, JE Stephens, RD Wiegel, ... Acta Crystallographica Section B: Structural Science 60 (6), 705-715, 2004 | 20 | 2004 |
| Apparatus and method of forming self-aligned cuts in mandrel and a non-mandrel lines of an array of metal lines G Bouche, JE Stephens US Patent 9,818,641, 2017 | 19 | 2017 |
| Methods, apparatus and system for a passthrough-based architecture G Bouche, TG Neogi, ACH Wei, Z Jia, J Kye, JE Stephens, IYL Lin, ... US Patent 9,818,651, 2017 | 18 | 2017 |
| Transistor contacts self-aligned in two dimensions ACH Wei, G Bouche, MA Zaleski, TG Neogi, JE Stephens, J Kye, Z Jia US Patent 9,202,751, 2015 | 18 | 2015 |
| Challenges of analog and I/O scaling in 10nm SoC technology and beyond A Wei, J Singh, G Bouche, M Zaleski, R Augur, B Senapati, J Stephens, ... 2014 IEEE international electron devices meeting, 18.3. 1-18.3. 4, 2014 | 17 | 2014 |
| Method of patterning pillars to form variable continuity cuts in interconnection lines of an integrated circuit JE Stephens, G Bouche US Patent 9,852,986, 2017 | 16 | 2017 |
| Method, apparatus and system for a high density middle of line flow Bouche, N Guillaume (Albany, NY), R Tuhin Guha (Fishkill, NY), ... US Patent 10,236,350, 2019 | 15 | 2019 |
| Forming cross-coupled line segments D Pritchard, JE Stephens US Patent 9,224,617, 2015 | 15 | 2015 |
| Apparatus and method of forming self-aligned cuts in a non-mandrel line of an array of metal lines JE Stephens, G Bouche US Patent 9,818,640, 2017 | 14 | 2017 |
| Methods of cross-coupling line segments on a wafer JE Stephens, L Yuan, LEI Lixia, D Pritchard, TG Neogi US Patent 9,472,455, 2016 | 14 | 2016 |
| Contact power rail JE Stephens, ML Tarabbia, NM Hindawy, RA Augur US Patent 8,946,914, 2015 | 14 | 2015 |
| Methods of forming a high-k contact liner to improve effective via separation distance and the resulting devices G Bouche, AC Wei, JE Stephens, DM Permana, J Vasudevan US Patent 9,825,031, 2017 | 13 | 2017 |
| Self-aligned double patterning via enclosure design Kye, L Jongwook (Seou, KR), S Harry J (Saratoga, NY), ... US Patent 8,839,168, 2014 | 12 | 2014 |
| Forming merged lines in a metallization layer by replacing sacrificial lines with conductive lines G Bouche, JE Stephens, V Chauhan, AC Wei US Patent 9,412,655, 2016 | 11 | 2016 |
| Borderless contact formation through metal-recess dual cap integration G Bouche, JE Stephens, TG Neogi, MA Zaleski, ACH Wei US Patent 9,502,528, 2016 | 10 | 2016 |
| Middle-of-the-line constructs using diffusion contact structures Rashed, M Mahbub (Santa Clara, CA), L Yuansheng (Santa Clara, CA), ... US Patent 9,006,100, 2015 | 10 | 2015 |
| Methods of forming a circuit that includes a cross-coupling gate contact structure wherein the circuit is to be manufactured using a triple patterning process L Yuan, JE Stephens, L Yang, SH Choi US Patent 8,969,199, 2015 | 10 | 2015 |
tuhin guha neogiIntelVerified email at intel.com
