Method and system for facilitating floorplanning for 3D IC S Sinha, CC Chiang US Patent 8,006,212, 2011 | 239 | 2011 |
Dummy filling technique for improved planarization of chip surface topography S Sinha, J Luo, CC Chiang US Patent 7,509,622, 2009 | 239 | 2009 |
Design for manufacturability and yield for nano-scale CMOS C Chiang, J Kawa Springer Science & Business Media, 2007 | 173 | 2007 |
Machine-learning-based hotspot detection using topological classification and critical feature extraction YT Yu, GH Lin, IHR Jiang, C Chiang Proceedings of the 50th annual design automation conference, 1-6, 2013 | 143 | 2013 |
Wirability of knock-knee layouts with 45 degrees wires C Chiang, M Sarrafzadeh IEEE Transactions on Circuits and Systems 38 (6), 613-624, 1991 | 121 | 1991 |
Global routing based on Steiner min-max trees C Chiang, M Sarrafzadeh, CK Wong IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 1990 | 117 | 1990 |
Simulating topography of a conductive material in a semiconductor wafer J Luo, Q Su, C Chiang US Patent 7,289,933, 2007 | 99 | 2007 |
Efficient process-hotspot detection using range pattern matching H Yao, S Sinha, C Chiang, X Hong, Y Cai Proceedings of the 2006 IEEE/ACM international conference on Computer-aided …, 2006 | 97 | 2006 |
SAPOR: Second-order Arnoldi method for passive order reduction of RCS circuits Y Su, J Wang, X Zeng, Z Bai, C Chiang, D Zhou IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004 …, 2004 | 92 | 2004 |
Accurate process-hotspot detection using critical design rule extraction YT Yu, YC Chan, S Sinha, IHR Jiang, C Chiang Proceedings of the 49th Annual Design Automation Conference, 1167-1172, 2012 | 89 | 2012 |
Moving cast shadow detection by exploiting multiple cues MT Yang, KH Lo, CC Chiang, WK Tai IET Image Processing 2 (2), 95-104, 2008 | 68 | 2008 |
Accurate detection for process-hotspots with vias and incomplete specification J Xu, S Sinha, CC Chiang 2007 IEEE/ACM International Conference on Computer-Aided Design, 839-846, 2007 | 63 | 2007 |
A powerful global router: based on Steiner min-max trees. CC Chiang, M Sarrafzadeh, CK Wong ICCAD, 2-5, 1989 | 61 | 1989 |
A weighted Steiner tree-based global router with simultaneous length and density minimization C Chiang, CK Wong, M Sarrafzadeh IEEE transactions on computer-aided design of integrated circuits and …, 1994 | 58 | 1994 |
The road to 3D EDA tool readiness C Chiang, S Sinha 2009 Asia and South Pacific Design Automation Conference, 429-436, 2009 | 57 | 2009 |
Identifying layout regions susceptible to fabrication issues by using range patterns S Sinha, H Yao, CC Chiang US Patent 7,503,029, 2009 | 55 | 2009 |
DRC-based hotspot detection considering edge tolerance and incomplete specification YT Yu, HR Jiang, Y Zhang, CC Chiang US Patent 9,594,867, 2017 | 53 | 2017 |
A layout dependent full-chip copper electroplating topography model J Luo, Q Su, C Chiang, J Kawa ICCAD-2005. IEEE/ACM International Conference on Computer-Aided Design, 2005 …, 2005 | 47 | 2005 |
Method and apparatus for performing RLC modeling and extraction for three-dimensional integrated circuit (3D-IC) designs Q Chen, B Qiu, CC Chiang, X Hu, M Koshy, B Biswas US Patent 8,146,032, 2012 | 45 | 2012 |
An IC manufacturing yield model considering intra-die variations J Luo, S Sinha, Q Su, J Kawa, C Chiang Proceedings of the 43rd annual Design Automation Conference, 749-754, 2006 | 44 | 2006 |