An efficient VLSI architecture design for logarithmic multiplication by using the improved operand decomposition D Nandan, J Kanungo, A Mahajan Integration 58, 134-141, 2017 | 37 | 2017 |
Enhanced performance of ultracapacitors using redox additive-based electrolytes D Jain, J Kanungo, SK Tripathi Applied Physics A 124, 1-14, 2018 | 36 | 2018 |
Enhancement in performance of supercapacitor using eucalyptus leaves derived activated carbon electrode with CH3COONa and HQ electrolytes: A step towards environment benign … D Jain, J Kanungo, SK Tripathi Journal of Alloys and Compounds 832, 154956, 2020 | 34 | 2020 |
An error-efficient Gaussian filter for image processing by using the expanded operand decomposition logarithm multiplication D Nandan, J Kanungo, A Mahajan Journal of ambient intelligence and humanized computing, 1-8, 2018 | 34 | 2018 |
Performance enhancement approach for supercapacitor by using mango kernels derived activated carbon electrode with p-hydroxyaniline based redox additive electrolyte D Jain, J Kanungo, SK Tripathi Materials Chemistry and Physics 229, 66-77, 2019 | 32 | 2019 |
An efficient VLSI architecture for iterative logarithmic multiplier D Nandan, J Kanungo, A Mahajan 2017 4th international conference on signal processing and integrated …, 2017 | 20 | 2017 |
Synergistic approach with redox additive for the development of environment benign hybrid supercapacitor D Jain, J Kanungo, SK Tripathi Journal of the Electrochemical Society 166 (14), A3168, 2019 | 15 | 2019 |
An efficient antilogarithmic converter by using 11-regions error correction scheme D Nandan, A Mahajan, J Kanungo 2017 4th international conference on signal processing, computing and …, 2017 | 13 | 2017 |
An Efficient VLSI architecture design for antilogarithmic converter by using the error correction scheme D Nandan, J Kanungo, A Mahajan IET Digital Library, 2016 | 13 | 2016 |
An efficient architecture of iterative logarithm multiplier D Nandan, J Kanungo, A Mahajan Int. J. Eng. Technol 7 (2.16), 24-28, 2018 | 11 | 2018 |
Performance analysis of a complete adiabatic logic system driven by the proposed power clock generator J Kanungo, S Dasgupta Journal of Semiconductors 35 (9), 095001, 2014 | 8 | 2014 |
Compact and errorless 16-region error correction scheme for antilogarithm converter D Nandan, K Kumar, J Kanungo, RK Mishra 2019 International Conference on Electrical, Electronics and Computer …, 2019 | 6 | 2019 |
65 years journey of logarithm multiplier D Nandan, J Kanungo, A Mahajan International journal of pure and applied mathematics 118 (14), 261-266, 2018 | 6 | 2018 |
Diminished-1 multiplier using modulo adder BK Patel, J Kanungo International Journal of Engineering & Technology 7 (4.20), 31-35, 2018 | 5 | 2018 |
An efficient architecture of leading one detector D Nandan, J Kanungo, A Mahajan International Journal of Pure and Applied Mathematics 118 (14), 267-272, 2018 | 4 | 2018 |
Single Phase Energy Recovery Logic and Conventional CMOS Logic: A Comparative Analysis J Kanungo, S Dasgupta Journal of Microelectronics and Solid State Electronics 2 (2A), 16-21, 2013 | 4 | 2013 |
Synergistic effect of redox couple VO2+/VO2+ with H3PO4 to enhance the supercapacitor performance D Jain, J Kanungo, SK Tripathi Journal of Materials Science: Materials in Electronics 30, 12244-12259, 2019 | 3 | 2019 |
Implementation of Leading One Detector based on reversible logic for logarithmic arithmetic D Nandan, J Kanungo, A Mahajan International Journal of Computer Applications 173 (8), 40-45, 2017 | 3 | 2017 |
Scaling trends in energy recovery logic: an analytical approach J Kanungo, S Dasgupta Journal of Semiconductors 34 (8), 085001, 2013 | 3 | 2013 |
Fabrication and characterization of supercapacitor comprising mango kernel derived electrode under different electrolyte system D Jain, SK Tripathi, J Kanungo, BL Gupta Energy Storage 5 (3), e465, 2023 | 2 | 2023 |