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Fang Cai
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Cited by
Year
Reduced-complexity decoder architecture for non-binary LDPC codes
X Zhang, F Cai
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, 1-10, 2010
1092010
Reliability-driven ECC allocation for multiple bit error resilience in processor cache
S Paul, F Cai, X Zhang, S Bhunia
IEEE Transactions on Computers 60 (1), 20-34, 2010
742010
Efficient partial-parallel decoder architecture for quasi-cyclic nonbinary LDPC codes
X Zhang, F Cai
Circuits and Systems I: Regular Papers, IEEE Transactions on, 1-1, 2011
722011
Low-Complexity Reliability-Based Message-Passing Decoder Architectures for Non-Binary LDPC Codes
X Zhang, F Cai, S Lin
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, 1-13, 0
66
Relaxed min-max decoder architectures for nonbinary low-density parity-check codes
F Cai, X Zhang
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 21 (11 …, 2012
552012
Partial-parallel decoder architecture for quasi-cyclic non-binary LDPC codes
X Zhang, F Cai
2010 IEEE International Conference on Acoustics, Speech and Signal …, 2010
312010
Finite alphabet iterative decoders for LDPC codes: Optimization, architecture and analysis
F Cai, X Zhang, D Declercq, SK Planjery, B Vasić
IEEE Transactions on Circuits and Systems I: Regular Papers 61 (5), 1366-1375, 2014
302014
Low-complexity architectures for reliability-based message-passing non-binary LDPC decoding
X Zhang, F Cai
2011 IEEE International Symposium of Circuits and Systems (ISCAS), 1303-1306, 2011
102011
Reduced-complexity extended Min-sum check node processing for non-binary LDPC decoding
X Zhang, F Cai
2010 53rd IEEE International Midwest Symposium on Circuits and Systems, 737-740, 2010
102010
Low-power ldpc decoding based on iteration prediction
X Zhang, F Cai, CJR Shi
2012 IEEE International Symposium on Circuits and Systems (ISCAS), 3041-3044, 2012
92012
Efficient check node processing architectures for non-binary LDPC decoding using power representation
F Cai, X Zhang
Journal of Signal Processing Systems 76, 211-222, 2014
82014
An Efficient Architecture for Iterative Soft Reliability-based Majority-logic Non-binary LDPC Decoding
X Zhang, F Cai
7*
Reduced-memory forward-backward check node processing architecture for non-binary LDPC decoding
X Zhang, F Cai
2011 IEEE 54th International Midwest Symposium on Circuits and Systems …, 2011
52011
Reduced-latency scheduling scheme for min-max non-binary LDPC decoding
X Zhang, F Cai
2010 IEEE Asia Pacific Conference on Circuits and Systems, 414-417, 2010
42010
Reduced-complexity check node processing for non-binary LDPC decoding
X Zhang, F Cai
2010 IEEE Workshop On Signal Processing Systems, 70-75, 2010
32010
Low-energy and low-latency error-correction for phase change memory
X Zhang, F Cai, MP Anantram
2013 IEEE International Symposium on Circuits and Systems (ISCAS), 1236-1239, 2013
12013
Low-Complexity decoding algorithms and architectures for non-binary LDPC codes
F Cai
Case Western Reserve University, 2013
12013
Efficient VLSI Architectures for Non-binary Low Density Parity Check Decoding
F Cai
Case Western Reserve University, 2011
2011
新型的基于 m 序列的复数训练序列生成方法
钟杰, 蔡昉, 赵民建
浙江大学学报: 工学版 43 (1), 108-110, 2009
2009
Efficient Check Node Processing Architectures for Non-binary LDPC Decoding Using Power Representation
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