| The Realization‐Independent Testing Based on the Black Box Fault Models E Bareiša, V Jusas, K Motiejūnas, R Šeinauskas Informatica 16 (1), 19-36, 2005 | 25 | 2005 |
| Tiesioginio sklidimo neuroninių tinklų taikymo daugiamačiams duomenims vizualizuoti tyrimai V Medvedev | 16 | 2008 |
| Test selection based on the evaluation of input stuck-at faults transmissions to output E Bareisa, R Seinauskas Information technology and control, Kaunas, Technologija 3 (2), 15-18, 1996 | 15 | 1996 |
| Generating functional delay fault tests for non-scan sequential circuits E Bareiša, V Jusas, L Motiejūnas, R Šeinauskas Information technology and control 39 (2), 2010 | 14 | 2010 |
| The use of a software prototype for verification test generation E Bareiša, V Jusas, K Motiejūnas, R Šeinauskas Information Technology and Control 37 (4), 2008 | 14 | 2008 |
| Functional delay clock fault models E Bareiša, V Jusas, K Motiejūnas, R Šeinauskas Information technology and control 37 (1), 2008 | 14 | 2008 |
| Functional delay test generation based on software prototype E Bareisa, V Jusas, K Motiejunas, R Seinauskas Microelectronics Reliability 49 (12), 1578-1585, 2009 | 12 | 2009 |
| Functional digital systems testing E Bareiša, V Jusas, K Motiejūnas, R Šeinauskas Kaunas, Technologija 281, 2006 | 12 | 2006 |
| Automatic test patterns generation for simulation-based validation V Jusas, R Seinauskas Proc. of the 8-th Biennal Baltic Electronics Conference, 6-9, 2002 | 11 | 2002 |
| A distance laboratory for computer-aided design R Seinauskas Proceedings of International Conference on Microelectronic Systems Education …, 1997 | 11 | 1997 |
| Circuit Reset Sequences based on Software Prototypes K Morkūnas, R Šeinauskas Elektronika ir Elektrotechnika 103 (7), 71-76, 2010 | 10 | 2010 |
| On the enrichment of functional delay fault tests E Bareiša, V Jusas, K Motiejūnas, R Šeinauskas Information technology and control 38 (3), 2009 | 9 | 2009 |
| Functional delay test construction approaches E Bareiša, V Jusas, K Motiejūnas, R Šeinauskas Elektronika ir Elektrotechnika 74 (2), 49-54, 2007 | 9 | 2007 |
| Procedures for selection of validation vectors on the algorithm level V Jusas, K Paulikas, R Šeinauskas Digest of papers of 2nd IEEE Latin-American Test Workshop.-Cancun, Mexico, 90-95, 2001 | 9 | 2001 |
| Test generation at the algorithm-level for gate-level fault coverage E Bareisa, V Jusas, K Motiejunas, R Seinauskas Microelectronics Reliability 48 (7), 1093-1101, 2008 | 8 | 2008 |
| Application of Functional Delay Tests for Testing of Transition Faults and Vice Versa E Bareiša, V Jusas, K Motiejūnas, R Šeinauskas Information Technology And Control 34 (2), 2005 | 8 | 2005 |
| Functional test generation based on combined random and deterministic search methods E Bareiša, V Jusas, K Motiejūnas, R Šeinauskas Informatica 18 (1), 3-26, 2007 | 7 | 2007 |
| Functional test generation remote tool E Bareisa, V Jusas, K Motiejunas, R Seinauskas 8th Euromicro Conference on Digital System Design (DSD'05), 192-195, 2005 | 7 | 2005 |
| The influence of circuit re-synthesizing on the fault coverage E Bareiša, V Jusas, K Motiejūnas, R Šeinauskas Information Technology and Control 31 (2), 2004 | 7 | 2004 |
| Procedures for Selection of Validation Vectors on the Algorithm Level. 2nd IEEE Latin-American Test Workshop, February 11-14, 2001 V Jusas, K Paulikas, R Seinauskas Cancun, Mexico, 90-95, 0 | 7 | |
