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Sriram Madhavan
Sriram Madhavan
Verified email at globalfoundries.com
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Feed-forward for silicon inspections (DFM2CFM: design to silicon) and feed-back for weakpoint predictor decks (CFM2DFM: silicon to design) guided by marker classification …
S SOMANI, S Madhavan, T Herrmann, S SCHÜLER, U Schroeder, ...
US Patent 10,095,826, 2018
104*2018
Growth of epitaxial a-axis and c-axis oriented Sr2RuO4 films
S Madhavan, BJ Gibbons, A Dabkowski, HA Dabkowska, ...
MRS Online Proceedings Library (OPL) 401, 1995
591995
Methods for quantitatively evaluating the quality of double patterning technology-compliant layouts
LT Wang, S Madhavan, L Capodieci
US Patent 8,516,407, 2013
202013
Framework for identifying recommended rules and DFM scoring model to improve manufacturability of sub-20nm layout design
P Pathak, S Madhavan, S Malik, LTN Wang, L Capodieci
Design for Manufacturability through Design-Process Integration VI 8327, 239-251, 2012
192012
Method for forming an integrated circuit device
K Ramkumar, CG Kallingal, S Madhavan
US Patent 6,534,378, 2003
152003
Methodology to extract, data mine and score geometric constructs from physical design layouts for analysis and applications in semiconductor manufacturing
P Pathak, K Krishnamoorthy, WL Wang, YC Lai, FE Gennari, S Somani, ...
Design-Process-Technology Co-optimization for Manufacturability X 9781, 77-88, 2016
142016
Optimization of self-aligned double patterning (SADP)-compliant layout designs using pattern matching for 10nm technology nodes and beyond
LTN Wang, UP Schroeder, Y Woo, J Zeng, S Madhavan, L Capodieci
Design-Process-Technology Co-optimization for Manufacturability X 9781, 98-106, 2016
102016
Growth of epitaxial Sr2RuO4 films and YBa2Cu3O7− δSr2RuO4 heterostructures
S Madhavan, JA Mitchell, T Nemoto, S Wozniak, Y Liu, DG Schlom, ...
Journal of crystal growth 174 (1-4), 417-423, 1997
101997
Electrical transport studies of epitaxial Sr2RuO4 films
Y Liu, JA Mitchell, S Madhavan, DG Schlom, A Dabkowski, ...
Czechoslovak Journal of Physics 46, 1113-1114, 1996
101996
Stitch insertion for reducing color density differences in double patterning technology (DPT)
L Wang, S Madhavan, L Capodieci
US Patent 8,918,745, 2014
92014
Body tie test structure for accurate body effect measurement
S Madhavan, Q Chen, DA Chan, JS Goo
US Patent 7,880,229, 2011
92011
Epitaxial Sr/sub 2/RuO/sub 4/heterostructures
S Madhavan, Y Liu, DG Schlom, A Dabkowski, HA Dabkowska, Y Suzuki, ...
IEEE transactions on applied superconductivity 7 (2), 2063-2066, 1997
81997
Deep learning-based hotspot prediction of via printability in process window corners
P Selvam, P Rezaeifakhr, UP Schroeder, J Bakshi, O Mohamed, ...
Design-Process-Technology Co-optimization XV 11614, 173-180, 2021
62021
Hybrid OPC flow with pattern search and replacement
P Verma, S Somani, YY Ping, P Pathak, RS Ghaida, CP Babcock, ...
Optical Microlithography XXVIII 9426, 254-261, 2015
62015
Pattern-based pre-OPC operation to improve model-based OPC runtime
P Verma, F Batarseh, S Somani, J Wang, S McGowan, S Madhavan
Photomask Technology 2014 9235, 21-31, 2014
62014
Deriving feature fail rate from silicon volume diagnostics data
S Malik, T Herrmann, S Madhavan, R Desineni, C Schuermyer, G Eide
IEEE Design & Test 30 (4), 26-34, 2013
52013
Automated yield enhancements implementation on full 28nm chip: challenges and statistics
S Malik, S Madhavan, P Pathak, L Capodieci, R Fathy, A Abdulghany
Design for Manufacturability through Design-Process Integration VI 8327, 269-277, 2012
52012
Foundry approach for layout risk assessment through comprehensive pattern harvesting and large-scale data analysis
MR Babu, S Song, Q Xie, P Rezaeifakhr, E Chiu, JH Park, D Ryan, ...
Design-Process-Technology Co-optimization for Manufacturability XIV 11328 …, 2020
42020
A methodology to optimize design pattern context size for higher sensitivity to hotspot detection using pattern association tree (PAT)
S Somani, P Pathak, P Verma, S Madhavan, L Capodieci
Design-Process-Technology Co-optimization for Manufacturability IX 9427, 212-224, 2015
42015
Timing variability analysis for layout-dependent-effects in 28nm custom and standard cell-based designs
P Hurat, RO Topaloglu, R Nachman, P Pathak, J Condella, S Madhavan, ...
Design for Manufacturability through Design-Process Integration V 7974, 310-322, 2011
42011
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