| Interfacing cores with on-chip packet-switched networks P Bhojwani, R Mahapatra 16th International Conference on VLSI Design, 2003. Proceedings., 382-387, 2003 | 84 | 2003 |
| IntellBatt: Towards smarter battery design SK Mandal, PS Bhojwani, SP Mohanty, RN Mahapatra Proceedings of the 45th annual Design Automation Conference, 872-877, 2008 | 48 | 2008 |
| A heuristic for peak power constrained design of network-on-chip (NoC) based multimode systems P Bhojwani, R Mahapatra, EJ Kim, T Chen 18th International Conference on VLSI Design held jointly with 4th …, 2005 | 34 | 2005 |
| Core network interface architecture and latency constrained on-chip communication P Bhojwani, RN Mahapatra 7th International Symposium on Quality Electronic Design (ISQED'06), 6 pp.-363, 2006 | 25 | 2006 |
| A robust protocol for concurrent on-line test (COLT) of NoC-based systems-on-a-chip PS Bhojwani, RN Mahapatra Proceedings of the 44th annual Design Automation Conference, 670-675, 2007 | 19 | 2007 |
| IntellBatt: Toward a smarter battery SK Mandal, RN Mahapatra, PS Bhojwani, SP Mohanty Computer 43 (3), 67-71, 2010 | 16 | 2010 |
| SAPP: Scalable and adaptable peak power management in NoCs PS Bhojwani, JD Lee, RN Mahapatra Proceedings of the 2007 international symposium on Low power electronics and …, 2007 | 12 | 2007 |
| An Infrastructure IP for online testing of network-on-chip based SoCs P Bhojwani, RN Mahapatra 8th International Symposium on Quality Electronic Design (ISQED'07), 867-872, 2007 | 11 | 2007 |
| Microprocessor Evaluations for Safety-Critical, Real-Time Applications: Authority for Expenditure No. 43 Phase 3 Report RN Mahapatra, P Bhojwani, JH Lee, Y Kim | 10 | 2009 |
| Robust concurrent online testing of network-on-chip-based SoCs PS Bhojwani, RN Mahapatra IEEE transactions on very large scale integration (VLSI) systems 16 (9 …, 2008 | 9 | 2008 |
| A safety analysis framework for COTS microprocessors in safety-critical applications JD Lee, PS Bhojwani, RN Mahapatra 10th IEEE High Assurance Systems Engineering Symposium (HASE'07), 407-408, 2007 | 5 | 2007 |
| Forward error correction for on-chip interconnection networks P Bhojwani, R Singhal, G Choi, R Mahapatra Unique Chips and Systems, 341-354, 2018 | 4 | 2018 |
| IntellBatt: The Smart Battery SK Mandal, PS Bhojwani, SP Mohanty, RN Mahapatra IEEE Computing Society, 2010 | 3 | 2010 |
| Communication Synthesis for on Chip Networks N Swaminathan, P Bhojwani, R Mahapatra Texas A & M University, 2002 | 3 | 2002 |
| A distributed concurrent on-line test scheduling protocol for many-core NoC-based systems JD Lee, RN Mahapatra, PS Bhojwani 2009 IEEE International Conference on Computer Design, 179-185, 2009 | 2 | 2009 |
| Mapping multimode system communication to a network-on-a-chip (NoC) PS Bhojwani Texas A&M University, 2004 | 2 | 2004 |
| An On-Demand Test Triggering Mechanism for NoC-Based Safety-Critical Systems JD Lee, N Gupta, PS Bhojwani, RN Mahapatra 9th International Symposium on Quality Electronic Design (isqed 2008), 184-189, 2008 | 1 | 2008 |
| IntellBatt SK Mandal, PS Bhojwani, SP Mohanty, RN Mahapatra Proceedings of the 45th annual Design Automation Conference, 2008 | | 2008 |
| Communication synthesis of networks-on-chip (NoC) PS Bhojwani Texas A&M University, 2007 | | 2007 |
| MAPPING MULTI-MODAL APPLICATIONS TO A NETWORK-ON-A-CHIP PS BHOJWANI Texas A&M University, 2003 | | 2003 |
Rabi MahapatraProfessor of Computer Science & Engg., Texas A&M UniversityVerified email at cse.tamu.edu
