| Automatic detection of human fall in video V Vishwakarma, C Mandal, S Sural Pattern Recognition and Machine Intelligence: Second International …, 2007 | 187 | 2007 |
| Performance comparison of AODV/DSR on-demand routing protocols for ad hoc networks in constrained situation R Misra, C Mandal Personal Wireless Communications, 2005. ICPWC 2005. 2005 IEEE International …, 2005 | 176 | 2005 |
| Minimum connected dominating set using a collaborative cover heuristic for ad hoc sensor networks R Misra, C Mandal IEEE Transactions on parallel and distributed systems 21 (3), 292-302, 2009 | 123 | 2009 |
| Ant-aggregation: ant colony algorithm for optimal data aggregation in wireless sensor networks R Misra, C Mandal 2006 IFIP International Conference on Wireless and Optical Communications …, 2006 | 107 | 2006 |
| An equivalence-checking method for scheduling verification in high-level synthesis C Karfa, D Sarkar, C Mandal, P Kumar IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2008 | 78 | 2008 |
| Rotation of CDS via connected domatic partition in ad hoc sensor networks R Misra, C Mandal Mobile Computing, IEEE Transactions on 8 (4), 488-499, 2009 | 76 | 2009 |
| GABIND: A GA Approach to Allocation and Binding for the High-Level Synthesis of Data Paths C Mandal, PP Chakrabarti, S Ghose IEEE Transactions on Very Large Scale Integration Systems 8 (6), 747-749, 2000 | 70 | 2000 |
| Verification of code motion techniques using value propagation K Banerjee, C Karfa, D Sarkar, C Mandal IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2014 | 69 | 2014 |
| Construction of minimum connected dominating set in wireless sensor networks using pseudo dominating set JP Mohanty, C Mandal, CMP Reade Ad Hoc Networks 42, 61-73, 2016 | 56 | 2016 |
| Formal verification of code motion techniques using data-flow-driven equivalence checking C Karfa, C Mandal, D Sarkar ACM Transactions on Design Automation of Electronic Systems (TODAES) 17 (3 …, 2012 | 53 | 2012 |
| A formal verification method of scheduling in high-level synthesis C Karfa, C Mandal, D Sarkar, SR Pentakota, CMP Reade 7th International Symposium on Quality Electronic Design (ISQED'06), 6 pp.-78, 2006 | 52 | 2006 |
| Complexity of fragmentable object bin packing and an application C Mandal, PP Chakrabarti, S Ghose Computers & Mathematics with Applications 35 (11), 91-97, 1998 | 52 | 1998 |
| Distributed Construction of Minimum Connected Dominating Set in Wireless Sensor Network Using Two-Hop Information JP Mohanty, C Mandal, CMP Reade Computer Networks, 2017 | 49 | 2017 |
| Verification of datapath and controller generation phase in high-level synthesis of digital circuits C Karfa, D Sarkar, C Mandal IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2010 | 40* | 2010 |
| Nano-scale CMOS analog circuits: models and CAD techniques for high-level design S Pandit, C Mandal, A Patra CRC Press, 2018 | 35* | 2018 |
| Verification of Loop and Arithmetic Transformations of Array-Intensive Behaviours C Karfa, K Banerjee, D Sarkar, C Mandal IEEE Transactions on CAD 32 (11), 1787--1800, 2013 | 35* | 2013 |
| An Improved Greedy Construction of Minimum Connected Dominating Sets in Wireless Networks A Das, M Aasawat, C Mandal, CMP Reade 2011 IEEE Wireless Communications and Networking Conference, 790-795, 2011 | 35 | 2011 |
| CURE: Consistent Update with Redundancy Reduction in SDN I Maity, A Mondal, S Misra, C Mandal IEEE Transactions on Communications, 2018 | 33 | 2018 |
| Efficient clusterhead rotation via domatic partition in self‐organizing sensor networks R Misra, C Mandal Wireless Communications and Mobile Computing 9 (8), 1040-1058, 2009 | 33* | 2009 |
| A design space exploration scheme for data-path synthesis C Mandal, PP Chakrabarti, S Ghose IEEE Transactions on Very Large Scale Integration (VLSI) Systems 7 (3), 331-338, 1999 | 32* | 1999 |
| Use of multi-port memories in programmable structures for architectural synthesis C Mandal, RM Zimmer 1996 Proceedings. Eighth Annual IEEE International Conference on Innovative …, 1996 | 30 | 1996 |
| Translation validation for PRES+ models of parallel behaviours via an FSMD equivalence checker S Bandyopadhyay, K Banerjee, D Sarkar, C Mandal Progress in VLSI Design and Test, 69-78, 2012 | 29* | 2012 |
| A genetic algorithm for the synthesis of structured data paths C Mandal, RM Zimmer VLSI Design 2000. Wireless and Digital Imaging in the Millennium …, 2000 | 28* | 2000 |
| Architecture of an Automatic program evaluation system AK Mandal, C Mandal, CMP Reade CSIE Proceedings, 2006 | 27* | 2006 |
| Web-Based Course Management and Web Services. C Mandal, VL Sinha, CMP Reade Electronic Journal of e-Learning 2 (1), 135-144, 2004 | 24 | 2004 |
| Allocation and binding in data path synthesis using a genetic algorithm approach C Mandal, PP Chakrabarti, S Ghose VLSI Design, 1996. Proceedings., Ninth International Conference on, 122-125, 1996 | 23* | 1996 |
| A virtual laboratory for computer organisation and logic design (COLDVL) and its utilisation for MOOCs G Roy, D Ghosh, C Mandal 2015 IEEE 3rd International Conference on MOOCs, Innovation and Technology …, 2015 | 22* | 2015 |
| Automated checking of the violation of precedence of conditions in else-if constructs in students' programs KK Sharma, K Banerjee, I Vikas, C Mandal 2014 IEEE International Conference on MOOC, Innovation and Technology in …, 2014 | 22* | 2014 |
| Video placement and disk load balancing algorithm for VoD proxy server A Nimkar, C Mandal, CMP Reade 2009 IEEE International Conference on Internet Multimedia Services …, 2009 | 19 | 2009 |
| Path Balanced Logic Design to Realise Block Ciphers Resistant to Power and Timing Attacks P De, C Mandal, U Parampalli IEEE Transactions on VLSI 27 (5), 1080–1092, 2019 | 18* | 2019 |
| Complexity Analysis and Algorithms for Data Path Synthesis C Mandal Indian Institute of Technology, 1995 | 18* | 1995 |
| DART: Data plane load reduction for traffic flow migration in SDN I Maity, S Misra, C Mandal IEEE Transactions on Communications 69 (3), 1765-1774, 2020 | 16 | 2020 |
| Extending the FSMD framework for validating code motions of array-handling programs K Banerjee, D Sarkar, C Mandal IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2014 | 16 | 2014 |
| CORE: Prediction-based control plane load reduction in software-defined IoT networks I Maity, S Misra, C Mandal IEEE Transactions on Communications 69 (3), 1835-1844, 2020 | 14 | 2020 |
| Tensor-based rule-space management system in SDN I Maity, A Mondal, S Misra, C Mandal IEEE Systems Journal 13 (4), 3921-3928, 2018 | 13 | 2018 |
| Equivalence checking of Petri net models of programs using static and dynamic cut-points S Bandyopadhyay, D Sarkar, C Mandal Acta Informatica, 2018 | 13 | 2018 |
| Systematic methodology for high-level performance modeling of analog systems S Pandit, C Mandal, A Patra 2009 22nd International Conference on VLSI Design, 361-366, 2009 | 13 | 2009 |
| Experimentation with SMT solvers and theorem provers for verification of loop and arithmetic transformations C Karfa, K Banerjee, D Sarkar, C Mandal Proceedings of the 5th IBM Collaborative Academia Research Exchange Workshop …, 2013 | 12* | 2013 |
| STAIRoute: Global Routing using Monotone Staircase Channels B Kar, S Sur-Kolay, C Mandal IEEE Computer Society Annual Symposium on VLSI, 90--95, 2013 | 12* | 2013 |
| A value propagation based equivalence checking method for verification of code motion techniques K Banerjee, C Karfa, D Sarkar, C Mandal IEEE International Symposium on System Design (ISED) 2012, 67-71, 2012 | 12 | 2012 |
| SamaTulyata: An Efficient Path Based Equivalence Checking Tool S Bandyopadhyay, S Sarkar, D Sarkar, C Mandal International Symposium on Automated Technology for Verification and Analysis, 2017 | 10 | 2017 |
| A virtual laboratory for basic electronics S Dhang, PK Jana, C Mandal Journal of Engineering, Science and Management Education 10 (1), 67-74, 2017 | 10 | 2017 |
| Self-healing for self-organizing cluster sensor networks R Misra, C Mandal 2006 Annual IEEE India Conference, 1-6, 2006 | 10 | 2006 |
| A distributed greedy algorithm for construction of minimum connected dominating set in wireless sensor network JP Mohanty, C Mandal 2014 Applications and Innovations in Mobile Computing (AIMoC), 104-110, 2014 | 8 | 2014 |
| A fast exploration procedure for analog high-level specification translation S Pandit, SK Bhattacharya, C Mandal, A Patra IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2008 | 8 | 2008 |
| A new approach to timing analysis using event propagation and temporal logic A Mondal, PP Chakrabarti, C Mandal Design, Automation and Test in Europe Conference and Exhibition, 2004 …, 2004 | 8 | 2004 |
| Deriving Bisimulation Relations from Path Extension Based Equivalence Checkers K Banerjee, D Sarkar, C Mandal IEEE Transactions on Software Engineering, 2016 | 7 | 2016 |
| Design and implementation of packet filter firewall using Binary Decision Diagram G Paul, A Pothnal, C Mandal, BB Bhattacharya Students' Technology Symposium (TechSym), 2011 IEEE, 17-22, 2011 | 7 | 2011 |
| A BDD-Based Design of an Area-Power Efficient Asynchronous Adder G Paul, R Reddy, C Mandal, BB Bhattacharya VLSI (ISVLSI), 2010 IEEE Computer Society Annual Symposium on, 29-34, 2010 | 7* | 2010 |
| Distinct pathoclinical clusters among patients with uncontrolled type 2 diabetes: results from a prospective study in rural India MR Aravindakshan, SK Maity, A Paul, P Chakrabarti, C Mandal, J Sarkar BMJ Open Diabetes Research and Care 10 (1), e002654, 2022 | 6 | 2022 |
| SCOPE: cost-efficient QoS-aware switch and controller placement in hybrid SDN I Maity, S Misra, C Mandal IEEE Systems Journal 16 (3), 4873-4880, 2021 | 6 | 2021 |
| Isolated systolic hypertension among the Bhotia of Uttaranchal CR Mandal, DK Adak, S Biswas, P Bharati Hum Biol Rev 1, 51-6, 2012 | 6 | 2012 |
| Revision of black soil map of india for sustainable crop production P Chandran, S Ray, C Mandal, D Mandal, J Prasad, D Sarkar, P Tiwary, ... National Seminar on Geospatial Solutions for Resource Conservation and …, 2012 | 6 | 2012 |
| Secure Path Balanced BDD-Based Pre-Charge Logic for Masking P De, U Parampalli, M Chittaranjan IEEE Transactions on Circuits and Systems I 67 (12), 4747 - 4760, 2020 | 5 | 2020 |
| Formal verification of movement authorities in automatic train control systems S Ghosh, P Dasgupta, C Mandal, A Katiyar The International Conference on Railway Engineering (ICRE) 2016, 1-8, 2016 | 5 | 2016 |
| Determining the User Intent Behind Web Search Queries by Learning from Past User Interactions with Search Results A Das, C Mandal, CMP Reade 19th International Conference on Management of Data, 2013 | 5 | 2013 |
| Workload driven power domain partitioning A Dobriyal, R Gonnabattula, P Dasgupta, C Mandal Progress in VLSI Design and Test, 147-155, 2012 | 5 | 2012 |
| Translation validation of loop and arithmetic transformations in the presence of recurrences K Banerjee, C Mandal, D Sarkar ACM SIGPLAN Notices 51 (5), 31-40, 2016 | 4 | 2016 |
| Global Routing using Monotone Staircases with Minimal Bends B Kar, S Sur-Kolay, C Mandal 2014 27th International Conference on VLSI Design and 2014 13th …, 2014 | 4 | 2014 |
| An automated high-level topology generation procedure for continuous-time ΣΔ modulator S Pandit, C Mandal, A Patra Integration 43 (3), 289-304, 2010 | 4 | 2010 |
| Sustainable maintenance of connected dominating set by solar energy harvesting for IoT networks CR Chowdhury, C Mandal, S Misra IEEE Transactions on Green Communications and Networking 6 (4), 2115-2127, 2022 | 3 | 2022 |
| ETHoS: Energy-aware traffic engineering for sustainable hybrid SDN I Maity, S Misra, C Mandal IEEE Transactions on Sustainable Computing 7 (4), 875-886, 2022 | 3 | 2022 |
| Traffic-aware consistent flow migration in SDN I Maity, S Misra, C Mandal ICC 2020-2020 IEEE International Conference on Communications (ICC), 1-6, 2020 | 3 | 2020 |
| POWER-SIM: An SOC simulator for estimating power profiles of mobile workloads P Ghosh, A Hazra, R Gonnabhaktula, N Bhilegaonkar, P Dasgupta, ... Journal of Low Power Electronics 8 (3), 293-303, 2012 | 3 | 2012 |
| Verification of register transfer level low power transformations C Karfa, C Mandal, D Sarkar 2011 IEEE Computer Society Annual Symposium on VLSI, 313-314, 2011 | 3 | 2011 |
| Register sharing verification during data-path synthesis C Karfa, C Mandal, D Sarkar, CMP Reade 2007 International Conference on Computing: Theory and Applications (ICCTA …, 2007 | 3 | 2007 |
| Verification of scheduling in high-level synthesis C Karfa, C Mandal, D Sarkar, SR Pentakota, CMP Reade IEEE Computer Society Annual Symposium on VLSI (ISVLSI) 2006, 141-146, 2006 | 3 | 2006 |
| Energy-Aware Service Allocation: A Crow Search-Based Approach CR Chowdhury, S Misra, C Mandal IEEE Transactions on Green Communications and Networking 7 (1), 211-223, 2022 | 2 | 2022 |
| Clustering Based Parameter Estimation of Thyroid Hormone Pathway D Ghosh, C Mandal IEEE/ACM Transactions on Computational Biology and Bioinformatics, 2020 | 2 | 2020 |
| COLDVL: a virtual laboratory tool with novel features to support learning in logic design and computer organisation G Roy, D Ghosh, C Mandal Journal of Computers in Education 4, 461-490, 2017 | 2 | 2017 |
| Connected Dominating Set in Wireless Sensor Network JP Mohanty, C Mandal Handbook of Research on Advanced Wireless Sensor Network Applications …, 2017 | 2 | 2017 |
| A translation validation framework for symbolic value propagation based equivalence checking of FSMDAs K Banerjee, C Mandal, D Sarkar Source Code Analysis and Manipulation (SCAM), 2015 IEEE 15th International …, 2015 | 2 | 2015 |
| Verification of KPN level Transformations C Karfa, D Sarkar, C Mandal 26th International Conference on VLSI Design, 338-343, 2013 | 2 | 2013 |
| Recipient specific electronic cash: a scheme for recipient specific yet anonymous and transferable electronic cash C Mandal, CMP Reade | 2 | 2007 |
| An Automatic Evaluation System with a Web Interface C Mandal, CMP Reade, VL Sinha, V Luxmi School of IT, IIT Kharagpur, India, Kingston Business School, Kingston …, 2004 | 2 | 2004 |
| SeamFlow: Seamless Flow Forwarding in Energy Harvesting-Enabled Access Points of SDWLAN CR Chowdhury, S Misra, C Mandal, S Bera IEEE Transactions on Sustainable Computing 8 (1), 94-108, 2022 | 1 | 2022 |
| IEEE 802.11 k-Based Lightweight, Distributed, and Cooperative Access Point Coverage Estimation Scheme in IoT Networks CR Chowdhury, S Misra, C Mandal IEEE Internet of Things Journal 9 (12), 10139-10148, 2021 | 1 | 2021 |
| Automatic Generation of Route Control Chart from Validated Signal Interlocking Plan A Das, M Gangwar, D Ghosh, C Mandal, A Sengupta, MM Waris IEEE Transactions on Intelligent Transportation Systems, 2020 | 1 | 2020 |
| Verification of Parallelizing Transformations of KPN Models C Karfa, D Sarkar, C Mandal IET Cyber-Physical Systems: Theory and Applications, 2019 | 1 | 2019 |
| SamaTulyataOne: A Path Based Equivalence Checker S Bandyopadhyay, D Sarkar, C Mandal Proceedings of the 12th Innovations in Software Engineering Conference …, 2019 | 1 | 2019 |
| Refresh Re-Use based Transparent Test for Detection of In-Field Permanent Faults in DRAMs B Ghoshal, C Mandal, I Sengupta Integration, the VLSI Journal, 2017 | 1 | 2017 |
| Layout validation using graph grammar and generation of yard specific safety properties for railway interlocking verification D Ghosh, C Mandal 2015 Asia-Pacific Software Engineering Conference (APSEC), 330-337, 2015 | 1 | 2015 |
| Location updates of mobile node in wireless sensor networks R Misra, C Mandal 2009 Fifth International Conference on Mobile Ad-hoc and Sensor Networks …, 2009 | 1 | 2009 |
| Asynchronous Design Methodology for an Efficient Implementation of Low power ALU P Manikandan, BD Liu, LY Chiou, G Sundar, C Mandal Circuits and Systems, 2006. APCCAS 2006. IEEE Asia Pacific Conference on …, 2006 | 1 | 2006 |
| A formal approach for high level synthesis of linear analog systems S Pandit, C Mandal, A Patra Proceedings of the 16th ACM Great Lakes symposium on VLSI, 345-348, 2006 | 1 | 2006 |
| Timing analysis of tree-like RLC circuits B Rajendran, V Kheterpal, A Das, J Majumder, C Mandal, PP Chakrabarti 2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat …, 2002 | 1 | 2002 |
| Register-interconnect optimization in data path synthesis C Mandal, PP Chakrabarti, S Ghose Microprocessing and microprogramming 33 (5), 279-288, 1992 | 1 | 1992 |
| DigiLoCS: A Leap Forward in Predictive Organ-on-Chip Simulations MR Aravindakshan, C Mandal, A Pothen, C Maass bioRxiv, 2024.03. 28.587123, 2024 | | 2024 |
| Parameter estimation for the oral minimal model and parameter distinctions between obese and non-obese type 2 diabetes MR ARAVINDAKSHAN, D Ghosh, C Mandal, KV Venkatesh, J Sarkar, ... medRxiv, 2024.04. 06.24305200, 2024 | | 2024 |
| Translation validation of coloured Petri net models of programs on integers S Bandyopadhyay, D Sarkar, C Mandal, H Giese Acta Informatica 59 (6), 725-759, 2022 | | 2022 |
| Exploring the Scope of Unconstrained Via Minimization by Recursive Floorplan Bipartitioning B Kar, S Sur-Kolay, C Mandal arXiv preprint arXiv:1811.05161, 2018 | | 2018 |
| Early Routability Assessment in VLSI Floorplans: A Generalized Routing Model B Kar, S Sur-Kolay, C Mandal arXiv preprint arXiv:1810.12789, 2018 | | 2018 |
| STAIRoute: Early Global Routing using Monotone Staircases for Congestion Reduction B Kar, S Sur-Kolay, C Mandal arXiv preprint arXiv:1810.10412, 2018 | | 2018 |
| Analysis of Aridity in Relation to Climate and Sustainability of Cotton Production in India. BP Bhaskar, PLA Satyavathi, C Mandal, SK Singh Not Available, 2017 | | 2017 |
| An Equivalence Checking Framework for Array-Intensive Programs K Banerjee, C Mandal, D Sarkar Automated Technology for Verification and Analysis: 15th International …, 2017 | | 2017 |
| Deriving bisimulation relations from path based equivalence checkers K Banerjee, D Sarkar, C Mandal Formal Aspects of Computing 29 (2), 365-379, 2017 | | 2017 |
| An early global routing framework for uniform wire distribution in SoCs B Kar, S Sur-Kolay, C Mandal 2016 29th IEEE International System-on-Chip Conference (SOCC), 139-144, 2016 | | 2016 |
| Combining BDD based Circuit Synthesis Technique with Masked Dual-Rail Pre-charge Logic to Eliminate Glitches in Circuits P De, U Parampalli, C Mandal 4TH ANNUAL DOCTORAL COLLOQUIUM, 42, 2016 | | 2016 |
| Digital Soil Resource Database and Information System GP Obi Reddy, D Sarkar, C Mandal, R Srivastava, T Bhattacharyya, ... Yes Dee Publishing Pvt. Ltd, Chennai, 2016 | | 2016 |
| A Novel EPE Aware Hybrid Global Route Planner after Floorplanning B Kar, S Sur-Kolay, C Mandal 2016 29th International Conference on VLSI Design and 2016 15th …, 2016 | | 2016 |
