R. Jacob Baker

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Vishal SaxenaUniversity of DelawareVerified email at udel.edu
Feng LinMicron Technology Inc.Verified email at micron.com
Yacouba Moumouni, Ph.D., FHEA, LE...Higher Colleges of Technology, UAEVerified email at hct.ac.ae
Yiyan LiFort Lewis CollegeVerified email at fortlewis.edu
Kris CampbellProfessor of Electrical and Computer Engineering, Boise State UniversityVerified email at boisestate.edu
Amy MollProfessor of Materials Science & Engineering, Boise State UniversityVerified email at boisestate.edu
David EstradaBoise State University; Idaho National LaboratoryVerified email at boisestate.edu
Richard G Southwick IIIResearch Staff Member, IBMVerified email at us.ibm.com
Maria MitkovaProfessor of Electrical and Computer Engineering Boise State UniversityVerified email at boisestate.edu
Molly M. GribbDean Elect, Caterpillar College of Engineering and Technology and Foster College of BusinessVerified email at bradley.edu
Sakkarapani BalagopalGraduate StudentVerified email at u.boisestate.edu
Amr HaggagDistinguished Technical Staff, Corporate Quality, Freescale SemiconductorVerified email at freescale.com
D PlumleeBoise State UniversityVerified email at boisestate.edu
Qawi Harvard

R. Jacob Baker

professor of electrical and computer engineering

Verified email at unlv.edu - Homepage

Electrical and Computer Engineering


Title Sort by citations Sort by year Sort by title	Cited by Cited by	Year
CMOS: circuit design, layout, and simulation RJ Baker Wiley-IEEE press, 2019	6314	2019
CMOS: mixed-signal circuit design RJ Baker john Wiley & sons, 2008	1094*	2008
Complementary bit PCRAM sense amplifier and method of operation G Hush, J Baker US Patent 6,791,859, 2004	302	2004
DRAM Circuit Design: Fundamental and High-Speed Topics B Keeth, RJ Baker, B Johnson, F Lin Wiley-IEEE Press, 2007	257	2007
Method and apparatus for adaptively adjusting the timing of a clock signal used to latch digital signals, and memory device using same RJ Baker, TA Manning US Patent 6,026,050, 2000	223	2000
Low skew differential receiver with disable feature B Keeth, RJ Baker US Patent 6,256,234, 2001	178	2001
PCRAM rewrite prevention J Moore, J Baker US Patent 6,909,656, 2005	177	2005
Optical interconnect in high-speed memory systems RJ Baker, B Keeth US Patent 7,941,056, 2011	167	2011
CMOS circuit design RJ Baker, HW Li, DE Boyce Layout and Simulation 3, 2005	162	2005
DRAM circuit design: a tutorial B Keeth, RJ Baker IEEE, 2001	136	2001
Method and apparatus for improving the performance of digital delay locked loop circuits JE Miller Jr, A Schoenfeld, M Ma, RJ Baker US Patent 6,069,506, 2000	123	2000
Transformerless capacitive coupling of gate signals for series operation of power MOS devices HL Hess, RJ Baker IEEE Transactions on Power Electronics 15 (5), 923-930, 2000	106	2000
Method and apparatus for adaptively adjusting the timing of a clock signal used to latch digital signals, and memory device using same RJ Baker, TA Manning US Patent 5,953,284, 1999	99	1999
A register-controlled symmetrical DLL for double-data-rate DRAM F Lin, J Miller, A Schoenfeld, M Ma, RJ Baker IEEE Journal of Solid-State Circuits 34 (4), 565-568, 1999	98	1999
Digital dual-loop DLL design using coarse and fine loops RJ Baker, F Lin US Patent 6,445,231, 2002	91	2002
Low skew differential receiver with disable feature B Keeth, RJ Baker US Patent 6,026,051, 2000	85	2000
High voltage pulse generation using current mode second breakdown in a bipolar junction transistor RJ Baker Review of scientific instruments 62 (4), 1031-1036, 1991	85	1991
Resistive memory element sensing using averaging RJ Baker US Patent 6,504,750, 2003	82	2003
Stacking power MOSFETs for use in high speed instrumentation RJ Baker, BP Johnson Review of scientific instruments 63 (12), 5799-5801, 1992	78	1992
Method and apparatus for sensing resistance values of memory cells RJ Baker US Patent 6,567,297, 2003	75	2003

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