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R. Jacob Baker
R. Jacob Baker
Professor of Electrical and Computer Engineering
Verified email at unlv.edu - Homepage
Title
Cited by
Cited by
Year
CMOS: circuit design, layout, and simulation
RJ Baker
Wiley-IEEE press, 2019
62072019
CMOS: mixed-signal circuit design
RJ Baker
john Wiley & sons, 2008
3822008
Complementary bit PCRAM sense amplifier and method of operation
G Hush, J Baker
US Patent 6,791,859, 2004
3022004
DRAM Circuit Design: Fundamental and High-Speed Topics
B Keeth, RJ Baker, B Johnson, F Lin
Wiley-IEEE Press, 2007
2522007
Method and apparatus for adaptively adjusting the timing of a clock signal used to latch digital signals, and memory device using same
RJ Baker, TA Manning
US Patent 6,026,050, 2000
2232000
CMOS circuit design, layout, and simulation
R Jacob Baker, HW Li, DE Boyce
IEEE Press, Wiley Jadhav MS, Borse S (2015) Adiabatic logic for low power …, 2008
1912008
Optical interconnect in high-speed memory systems
RJ Baker, B Keeth
US Patent 7,941,056, 2011
1772011
PCRAM rewrite prevention
J Moore, J Baker
US Patent 6,909,656, 2005
1772005
Low skew differential receiver with disable feature
B Keeth, RJ Baker
US Patent 6,256,234, 2001
1722001
CMOS circuit design
RJ Baker, HW Li, DE Boyce
Layout and Simulation 3, 2005
1682005
DRAM circuit design: a tutorial
B Keeth, RJ Baker
IEEE, 2001
1332001
Method and apparatus for improving the performance of digital delay locked loop circuits
JE Miller Jr, A Schoenfeld, M Ma, RJ Baker
US Patent 6,069,506, 2000
1232000
Transformerless capacitive coupling of gate signals for series operation of power MOS devices
HL Hess, RJ Baker
IEEE Transactions on Power Electronics 15 (5), 923-930, 2000
1042000
Method and apparatus for adaptively adjusting the timing of a clock signal used to latch digital signals, and memory device using same
RJ Baker, TA Manning
US Patent 5,953,284, 1999
991999
A register-controlled symmetrical DLL for double-data-rate DRAM
F Lin, J Miller, A Schoenfeld, M Ma, RJ Baker
IEEE Journal of Solid-State Circuits 34 (4), 565-568, 1999
971999
Digital dual-loop DLL design using coarse and fine loops
RJ Baker, F Lin
US Patent 6,445,231, 2002
912002
Low skew differential receiver with disable feature
B Keeth, RJ Baker
US Patent 6,026,051, 2000
852000
High voltage pulse generation using current mode second breakdown in a bipolar junction transistor
RJ Baker
Review of scientific instruments 62 (4), 1031-1036, 1991
841991
Resistive memory element sensing using averaging
RJ Baker
US Patent 6,504,750, 2003
822003
Stacking power MOSFETs for use in high speed instrumentation
RJ Baker, BP Johnson
Review of scientific instruments 63 (12), 5799-5801, 1992
761992
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