Embedded-memory test and repair: infrastructure IP for SoC yield Y Zorian, S Shoukourian IEEE Design and Test of Computers, 58-66, 2003 | 344 | 2003 |
SoC yield optimization via an embedded-memory test and repair infrastructure S Shoukourian, V Vardanian, Y Zorian IEEE Design & Test of Computers 21 (3), 200-207, 2004 | 94 | 2004 |
Experimental study on Hamming and Hsiao codes in the context of embedded applications G Tshagharyan, G Harutyunyan, S Shoukourian, Y Zorian 2017 IEEE East-West Design & Test Symposium (EWDTS), 1-4, 2017 | 48 | 2017 |
An approach for evaluation of redundancy analysis algorithms S Shoukourian, V Vardanian, Y Zorian Proceedings 2001 IEEE International Workshop on Memory Technology, Design …, 2001 | 48 | 2001 |
A robust solution for embedded memory test and repair K Darbinyan, G Harutyunyan, S Shoukourian, V Vardanian, Y Zorian 2011 Asian Test Symposium, 461-462, 2011 | 37 | 2011 |
A new method for march test algorithm generation and its application for fault detection in RAMs G Harutyunyan, S Shoukourian, V Vardanian, Y Zorian IEEE Transactions on computer-aided design of integrated circuits and …, 2012 | 33 | 2012 |
A methodology for design and evaluation of redundancy allocation algorithms S Shoukourian, VA Vardanian, Y Zorian 22nd IEEE VLSI Test Symposium, 2004. Proceedings., 249-255, 2004 | 27 | 2004 |
Memory physical aware multi-level fault diagnosis flow G Harutyunyan, S Martirosyan, S Shoukourian, Y Zorian IEEE Transactions on Emerging Topics in Computing 8 (3), 700-711, 2018 | 21 | 2018 |
Various methods and apparatuses for memory modeling using a structural primitive verification for memory compilers K Aleksanyan, K Amirkhanyan, S Karapetyan, A Shubat, S Shoukourian, ... US Patent 8,112,730, 2012 | 20 | 2012 |
Symmetry measure for memory test and its application in BIST optimization G Harutyunyan, A Hakhumyan, S Shoukourian, VA Vardanian, Y Zorian Journal of Electronic Testing 27, 753-766, 2011 | 17 | 2011 |
Generic BIST architecture for testing of content addressable memories H Grigoryan, G Harutyunyan, S Shoukourian, V Vardanian, Y Zorian 2011 IEEE 17th International On-Line Testing Symposium, 86-91, 2011 | 17 | 2011 |
Overview study on fault modeling and test methodology development for FinFET-based memories G Tshagharyan, G Harutyunyan, S Shoukourian, Y Zorian 2015 IEEE East-West Design & Test Symposium (EWDTS), 1-4, 2015 | 16 | 2015 |
Fault awareness for memory BIST architecture shaped by multidimensional prediction mechanism G Harutyunyan, S Shoukourian, Y Zorian IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2018 | 15 | 2018 |
Test solutions for nanoscale Systems-on-Chip: Algorithms, methods and test infrastructure Y Zorian, S Shoukourian Ninth International Conference on Computer Science and Information …, 2013 | 15 | 2013 |
Testing electronic memories based on fault and test algorithm periodicity A Hakhumyan, G Harutyunyan, S Shoukourian, V Vardanian, Y Zorian US Patent App. 13/183,468, 2013 | 14 | 2013 |
An effective solution for building memory BIST infrastructure based on fault periodicity G Harutyunyan, S Shoukourian, V Vardanian, Y Zorian 2013 IEEE 31st VLSI Test Symposium (VTS), 1-6, 2013 | 13 | 2013 |
The equivalence problem of multidimensional multitape automata H Grigorian, S Shoukourian Journal of Computer and System Sciences 74 (7), 1131-1138, 2008 | 13 | 2008 |
Memory modeling using an intermediate level structural description K Aleksanyan, K Amirkhanyan, S Shoukourian, V Vardanian, Y Zorian US Patent 7,768,840, 2010 | 12 | 2010 |
Extending fault periodicity table for testing faults in memories under 20nm G Harutyunyan, S Shoukourian, V Vardanian, Y Zorian Proceedings of IEEE East-West Design & Test Symposium (EWDTS 2014), 1-4, 2014 | 10 | 2014 |
The equivalence problem of deterministic multitape finite automata: a new proof of solvability using a multidimensional tape AA Letichevsky, AS Shoukourian, SK Shoukourian Language and Automata Theory and Applications: 4th International Conference …, 2010 | 10 | 2010 |