| 8.5 a scalable adaptive ADC/DSP-based 1.25-to-56Gbps/112Gbps high-speed transceiver architecture using decision-directed MMSE CDR in 16nm and 7nm D Xu, Y Kou, P Lai, Z Cheng, TY Cheung, L Moser, Y Zhang, X Liu, ... 2021 IEEE International Solid-State Circuits Conference (ISSCC) 64, 134-136, 2021 | 28 | 2021 |
| A 140-mV variation-tolerant deep sub-threshold SRAM in 65-nm CMOS K Sarfraz, J He, M Chan IEEE Journal of Solid-State Circuits 52 (8), 2215-2220, 2017 | 17 | 2017 |
| Modeling CNTFET performance variation due to spatial distribution of carbon nanotubes Z Ahmed, L Zhang, K Sarfraz, M Chan IEEE Transactions on Electron Devices 63 (9), 3776-3781, 2016 | 7 | 2016 |
| A 1.2 V-to-0.4 V 3.2 GHz-to-14.3 MHz power-efficient 3-port register file in 65-nm CMOS K Sarfraz, M Chan IEEE Transactions on Circuits and Systems I: Regular Papers 64 (2), 360-372, 2016 | 6 | 2016 |
| Characterization of a low leakage current and high-speed 7T SRAM circuit with wide voltage margins K Sarfraz, V Kursun 2013 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 64-69, 2013 | 6 | 2013 |
| A 65nm 3.2GHz 44.2mW Low-Vt register file with robust low-capacitance dynamic local bitlines K Sarfraz, M Chan ESSCIRC Conference 2015-41st European Solid-State Circuits Conference …, 2015 | 5 | 2015 |
| Comparison of two SRAM matrix leakage reduction techniques in 45nm technology K Sarfraz 2010 International Conference on Microelectronics, 367-370, 2010 | 4 | 2010 |
| Low voltage SRAM design using tunneling regime of CNTFET Z Ahmed, K Sarfraz, L Zhang, M Chan 14th IEEE International Conference on Nanotechnology, 864-867, 2014 | 3 | 2014 |
| A low-noise local bitline technique for dual-Vt register files K Sarfraz, M Chan 2014 IEEE Faible Tension Faible Consommation, 1-4, 2014 | 3 | 2014 |
| A compact low-power 4-port register file with grounded write bitlines and single-ended read operations K Sarfraz, M Chan Integration 55, 12-21, 2016 | 1 | 2016 |
| Write ability enhancement techniques for L1 cache on next-generation IBM POWERTM processors K Sarfraz, M Chan 2015 IEEE International Conference on Electron Devices and Solid-State …, 2015 | 1 | 2015 |
| A novel low-leakage 8T differential SRAM cell K Sarfraz 2011 IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, 19-24, 2011 | 1 | 2011 |
| SRAM POWER REDUCTION–AN ULTRA-LOW-POWER SRAM ARCHITECTURE IN 45nm TECHNOLOGY K Sarfraz, NP van der Meijs, TS Doorn, RW Salters Master Thesis 2009, 2009 | 1 | 2009 |
| An Efficient 6TP SRAM-Based CIM Macro With Column ADCs for Binarized Neural Networks I Shah, K Sarfraz, M Chan IEEE Transactions on Circuits and Systems II: Express Briefs, 2024 | | 2024 |
| A Scalable Adaptive ADC/DSP-Based 1.25-to-56Gbps/112Gbps High-Speed Transceiver Architecture Using Decision-Directed MMSE CDR in 16nm and 7nm KKC D. Xu, Y. Kou, P. Lai, Z. Cheng, T. Y. Cheung, L. Moser, Y. Zhang, X ... Proceedings of the International Solid-State Circuits Conference (ISSCC) 64, 2021 | | 2021 |
| A voltage-scalable zero-delay-overhead scheme for standby power reduction in dynamic register files K Sarfraz, M Chan 2016 IEEE 59th International Midwest Symposium on Circuits and Systems …, 2016 | | 2016 |
| Modeling spatial distribution induced variability in CNT array based FETs Z Ahmed, L Zhang, K Sarfraz, MS Chan | | 2016 |
| Power Efficient Cache Memories with Wide Operating Voltage Range K Sarfraz PQDT-Global, 2016 | | 2016 |
| Nanoscale register file circuit design—Challenges and opportunities K Sarfraz, M Chan 2015 IEEE 11th International Conference on ASIC (ASICON), 1-4, 2015 | | 2015 |
| An area-efficient 1.5-GHz dual-VDD4-port register file for real-time microprocessors K Sarfraz, M Chan 2015 IEEE International Conference on Electron Devices and Solid-State …, 2015 | | 2015 |
Mansun ChanChair Professor, HKUSTVerified email at ust.hk
