| Logical modelling of delay degradation effect in static CMOS gates MVJLH MJ Bellido-Diaz J Juan-Chico, AJ Acosta IEE Proceedings-Circuits, Devices and Systems 147 (2), 107-117, 2000 | 89 | 2000 |
| Python as a hardware description language: A case study JI Villar, J Juan, MJ Bellido, J Viejo, D Guerrero, J Decaluwe 2011 VII Southern Conference on Programmable Logic (SPL), 117-122, 2011 | 42 | 2011 |
| Simple binary random number generator MJ Bellido, AJ Acosta, M Valencia, A Barriga, JL Huertas Electronics Letters 7 (28), 617-618, 1992 | 42 | 1992 |
| Logic-timing simulation and the degradation delay model MJ Bellido, JJ Chico, M Valencia Imperial College Press, 2006 | 36 | 2006 |
| SODS: A new CMOS differential-type structure AJ Acosta, M Valencia, A Barriga, MJ Bellido, JL Huertas IEEE journal of solid-state circuits 30 (7), 835-838, 1995 | 32 | 1995 |
| Problemas de circuitos y sistemas digitales CB Oliva, MJB Díaz, AJM Cantero, MPP Fernández, MV Barrero McGraw-Hill, 1997 | 28 | 1997 |
| Inertial and degradation delay model for CMOS logic gates J Juan-Chico, PR de Clavijo, MJ Bellido, AJ Acosta, M Valenia 2000 IEEE International Symposium on Circuits and Systems (ISCAS) 1, 459-462, 2000 | 26 | 2000 |
| Degradation delay model extension to CMOS gates J Juan-Chico, MJ Bellido, P Ruiz-de-Clavijo, AJ Acosta, M Valencia Integrated Circuit Design: Power and Timing Modeling, Optimization and …, 2000 | 23 | 2000 |
| A simple binary random number generator: new approaches for cmos vlsi MJ Bellido, AJ Acosta, M Valencia, A Barriga, JL Huertas [1992] Proceedings of the 35th Midwest Symposium on Circuits and Systems …, 1992 | 21 | 1992 |
| HALOTIS: High accuracy logic timing simulator with inertial and degradation delay model PR de Clavijo Vazquez, J Juan-Chico, MJ Bellido, A Acosta, M Valencia Proceedings Design, Automation and Test in Europe. Conference and Exhibition …, 2001 | 19 | 2001 |
| Design and characterisation of a CMOS VLSI self-timed multiplier architecture based on a bit-level pipelined-array structure AJ Acosta, R Jiménez, A Barriga, MJ Bellido, M Valencia, JL Huertas IEE Proceedings-Circuits, Devices and Systems 145 (4), 247-253, 1998 | 17 | 1998 |
| Analysis of metastable operation in a CMOS dynamic D-latch J Juan-Chico, MJ Bellido, AJ Acosta, M Valencia, JL Huertas Analog Integrated Circuits and Signal Processing 14, 143-157, 1997 | 17 | 1997 |
| Characterization of normal propagation delay for delay degradation model (DDM) A Millán, J Juan, MJ Bellido, P Ruiz-de-Clavijo, D Guerrero International Workshop on Power and Timing Modeling, Optimization and …, 2002 | 16 | 2002 |
| Measurement of the switching activity of CMOS digital circuits at the gate level C Baena, J Juan-Chico, MJ Bellido, PR de Clavijo, CJ Jimenez, ... Integrated Circuit Design. Power and Timing Modeling, Optimization and …, 2002 | 16 | 2002 |
| Delay degradation effect in submicronic CMOS inverters J Juan Chico, MJ Bellido Díaz, AJ Acosta Jiménez, Á Barriga Barros, ... PATMOS 1997: 6th International Workshop on Power and Timing Modeling …, 1997 | 15 | 1997 |
| Un ejemplo de implemetación de una distribución Linux en un SoC basado en hardware Linux A Muñoz, E Ostúa, P Ruiz, MJ Bellido, J Viejo, A Millan, J Juan, ... Proc. Actas de las IV JCRA, 85-92, 2007 | 14 | 2007 |
| Building a SoC for industrial applications based on LEON microprocessor and a GNU/Linux distribution A Muñoz, E Ostua, MJ Bellido, A Millan, J Juan, D Guerrero 2008 IEEE International Symposium on Industrial Electronics, 1727-1732, 2008 | 13 | 2008 |
| Modular asynchronous arbiter insensitive to metastability M Valencia, MJ Bellido, JL Huertas, AJ Acosta, S Sánchez-Solano IEEE transactions on computers 44 (12), 1456-1461, 1995 | 13 | 1995 |
| Efficient design and implementation on FPGA of a MicroBlaze peripheral for processing direct electrical networks measurements J Viejo, MJ Bellido, A Millán, E Ostúa, J Juan, P Ruiz-de-Clavijo, ... 2006 International Symposium on Industrial Embedded Systems, 1-7, 2006 | 12 | 2006 |
| Design and implementation of a SNTP client on FPGA J Viejo, J Juan, MJ Bellido, E Ostua, A Millan, P Ruiz-de-Clavijo, A Munoz, ... 2008 IEEE International Symposium on Industrial Electronics, 1971-1975, 2008 | 11 | 2008 |
Jorge JuanProfesor Titular de Universidad, Universidad de Sevilla, EspañaVerified email at dte.us.es
