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Vaibhav Jain
Vaibhav Jain
ABES Institute of Technology
Verified email at abesit.in
Title
Cited by
Cited by
Year
Area and energy optimized multilayer QCA-based 4N-bit scalable multiplier (M4N-MUL)
V Jain, DK Sharma, HM Gaur
The European Physical Journal Plus 137 (11), 1281, 2022
82022
Comprehensive and Comparative Analysis of QCA-based Circuit Designs for Next-generation Computation
V Jain, DK Sharma, HM Gaur, AK Singh, X Wen
ACM Computing Surveys 56 (5), 1-36, 2023
72023
Fault-tolerant design of shift register using multilayer crossover in QCA
V Jain, DK Sharma, HM Gaur
The European Physical Journal Plus 138 (5), 453, 2023
32023
Faster access cost-efficient design of RAM cell using multilayer crossover in QCA
V Jain, DK Sharma, HM Gaur
The European Physical Journal Plus 138 (3), 190, 2023
32023
Cost optimized design of full adder in qca technology
P Paramjeet, S Gupta, V Jain, HM Gaur
2022 3rd International Conference on Computing, Analytics and Networks (ICAN …, 2022
22022
Digital Simulation of Limit Cycle in Second and Higher Order Analog Filter using MATLAB
V Jain, D Garg, AK Arora
International Journal of Computer Applications 53 (2), 2012
12012
Fast cost efficient Magnitude Comparator using RMG in QCA
V Jain, DK Sharma, HM Gaur
2023 3rd International conference on Artificial Intelligence and Signal …, 2023
2023
Optimized Full Adder-Subtractor in QCA for nano-computing applications
V Jain, DK Sharma, HM Gaur
2023 6th International Conference on Information Systems and Computer …, 2023
2023
An Optimized Approach of Designing Register and Counter in QCA
V Jain, DK Sharma, HM Gaur
Quantum-Dot Cellular Automata Circuits for Nanocomputing Applications, 131-164, 0
An Optimized Approach of Designing Adders and Multiplexer in QCA
V Jain, DK Sharma, HM Gaur
Quantum-Dot Cellular Automata Circuits for Nanocomputing Applications, 63-98, 0
Digital Simulation of Limit Cycle in Second & Higher Order Analog Filter
V Jain, D Garg
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