Tuning the Schottky barrier height of nickel silicide on p-silicon by aluminum segregation M Sinha, EF Chor, YC Yeo Applied Physics Letters 92 (22), 2008 | 58 | 2008 |
Achieving sub-0.1 eV hole Schottky barrier height for NiSiGe on SiGe by aluminum segregation M Sinha, RTP Lee, A Lohani, S Mhaisalkar, EF Chor, YC Yeo Journal of The Electrochemical Society 156 (4), H233, 2009 | 20 | 2009 |
Novel Aluminum Segregation at NiSi/ -Si Source/Drain Contact for Drive Current Enhancement in -Channel FinFETs M Sinha, RTP Lee, KM Tan, GQ Lo, EF Chor, YC Yeo IEEE electron device letters 30 (1), 85-87, 2008 | 18 | 2008 |
Contact resistance reduction technology using aluminum implant and segregation for strained p-FinFETs with silicon–germanium source/drain M Sinha, RTP Lee, EF Chor, YC Yeo IEEE Transactions On Electron Devices 57 (6), 1279-1286, 2010 | 14 | 2010 |
Schottky barrier height tuning of silicide on Si1− xCx M Sinha, EF Chor, CF Tan Applied Physics Letters 91 (24), 2007 | 14 | 2007 |
Single silicide comprising Nickel-Dysprosium alloy for integration in p-and n-FinFETs with independent control of contact resistance by Aluminum implant M Sinha, RTP Lee, SN Devi, GQ Lo, EF Chor, YC Yeo 2009 Symposium on VLSI Technology, 106-107, 2009 | 10 | 2009 |
Nickel-silicide contact technology with dual near-band-edge barrier heights and integration in CMOS FinFETs with single mask M Sinha, EF Chor, YC Yeo IEEE electron device letters 31 (9), 918-920, 2010 | 9 | 2010 |
Schottky barrier height modulation of Nickel–dysprosium-alloy germanosilicide contacts for strained P-FinFETs M Sinha, RTP Lee, EF Chor, YC Yeo IEEE electron device letters 30 (12), 1278-1280, 2009 | 9 | 2009 |
Silicon: Carbon source/drain stressors: Integration of a novel nickel aluminide-silicide and post-solid-phase-epitaxy anneal for reduced Schottky-barrier and leakage SM Koh, WJ Zhou, RTP Lee, M Sinha, CM Ng, Z Zhao, H Maynard, ... ECS Transactions 25 (7), 211, 2009 | 7 | 2009 |
Effect of substitutional carbon concentration on Schottky-barrier height of nickel silicide formed on epitaxial silicon-carbon films PSY Lim, RTP Lee, M Sinha, DZ Chi, YC Yeo Journal of Applied Physics 106 (4), 2009 | 5 | 2009 |
Integration of Al segregated NiSiGe/SiGe source/drain contact technology in p-FinFETs for drive current enhancement M Sinha, RTP Lee, SN Devi, GQ Lo, EF Chor, YC Yeo ECS Transactions 19 (1), 323, 2009 | 5 | 2009 |
Stress memorization techniques for transistor devices M Sinha, P Kannan, XU Cuiqin, T Wang, SK Regonda US Patent 9,741,853, 2017 | 2 | 2017 |
Sulfur implant for reducing nickel silicide contact resistance in FinFETs with silicon-carbon source/drain SM Koh, M Sinha, Y Tong, HC Chin, WW Fang, X Zhang, CM Ng, ... 2009 International Semiconductor Device Research Symposium, 1-2, 2009 | 2 | 2009 |
p-FinFETs with Al segregated NiSi/p+-Si source/drain contact junction for series resistance reduction M Sinha, RTP Lee, SN Devi, GQ Lo, EF Chor, YC Yeo 2009 International Symposium on VLSI Technology, Systems, and Applications …, 2009 | 2 | 2009 |
Heterostructure PIN Rectifier Diode For Power Applications B Mazhari, M Sinha, J Dixit 2005 IEEE Conference on Electron Devices and Solid-State Circuits, Hong Kong …, 2005 | 2 | 2005 |
Nickel silicide in bipolar complementary-metal-oxide-semiconductor (BiCMOS) device and method of manufacturing M Sinha, E Preisler, DJ Howard US Patent 11,276,682, 2022 | 1 | 2022 |
Method of Manufacturing Nickel Silicide in Bipolar Complementary-Metal-Oxide-Semiconductor (BiCMOS) M Sinha, E Preisler, DJ Howard US Patent App. 17/404,916, 2022 | | 2022 |
Nickel Silicide in Bipolar Complementary-Metal-Oxide-Semiconductor (BiCMOS) Device M Sinha, E Preisler, DJ Howard US Patent App. 17/464,046, 2022 | | 2022 |
Method of Manufacturing Bipolar Complementary-Metal-Oxide-Semiconductor (BiCMOS) Devices Using Nickel Silicide M Sinha, E Preisler, DJ Howard US Patent App. 17/465,246, 2022 | | 2022 |
Schottky barrier engineering for contact resistance reduction in nanoscale CMOS transistors M SINHA | | 2010 |