| Designing logic circuits for probabilistic computation in the presence of noise K Nepal, RI Bahar, J Mundy, WR Patterson, A Zaslavsky Design Automation Conference, 2005. Proceedings. 42nd, 485-490, 2005 | 113 | 2005 |
| Apnea detection and respiration rate estimation through parametric modelling K Nepal, E Biegeleisen, T Ning Proceedings of the IEEE 28th annual northeast bioengineering conference …, 2002 | 74 | 2002 |
| Design of a ternary static memory cell using carbon nanotube-based transistors K You, K Nepal Micro & Nano Letters, IET 6 (6), 381-385, 2011 | 51 | 2011 |
| Using implications for online error detection K Nepal, N Alves, J Dworak, RI Bahar Test Conference, 2008. ITC 2008. IEEE International, 1-10, 2008 | 45 | 2008 |
| A cost effective approach for online error detection using invariant relationships N Alves, A Buben, K Nepal, J Dworak, RI Bahar Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions …, 2010 | 40 | 2010 |
| Designing nanoscale logic circuits based on markov random fields K Nepal, RI Bahar, J Mundy, WR Patterson, A Zaslavsky Journal of Electronic Testing 23, 255-266, 2007 | 40 | 2007 |
| Optimizing noise-immune nanoscale circuits using principles of Markov random fields K Nepal, RI Bahar, J Mundy, WR Patterson, A Zaslavsky Proceedings of the 16th ACM Great Lakes symposium on VLSI, 149-152, 2006 | 23 | 2006 |
| Designing MRF based error correcting circuits for memory elements K Nepal, RI Bahar, J Mundy, WR Patterson, A Zaslavsky Design, Automation and Test in Europe, 2006. DATE'06. Proceedings 1, 1-2, 2006 | 23 | 2006 |
| Noise margin-optimized ternary CMOS SRAM delay and sizing characteristics Z Kamar, K Nepal 2010 53rd IEEE International Midwest Symposium on Circuits and Systems, 801-804, 2010 | 21 | 2010 |
| Enhancing online error detection through area-efficient multi-site implications N Alves, Y Shi, J Dworak, RI Bahar, K Nepal VLSI Test Symposium (VTS), 2011 IEEE 29th, 241-246, 2011 | 20 | 2011 |
| MRF reinforcer: A probabilistic element for space redundancy in nanoscale circuits K Nepal, RI Bahar, J Muddy, WR Patterson, A Zaslavsky Micro, IEEE 26 (5), 19-27, 2006 | 16 | 2006 |
| Dynamic circuits for ternary computation in carbon nanotube based field effect transistors K Nepal NEWCAS Conference (NEWCAS), 2010 8th IEEE International, 53-56, 2010 | 15 | 2010 |
| Carbon nanotube field effect transistor-based content addressable memory architectures K Nepal, K You IEE, 2012 | 14 | 2012 |
| Techniques for designing noise-tolerant multi-level combinational circuits K Nepal, RI Bahar, J Mundy, WR Patterson, A Zaslavsky 2007 Design, Automation & Test in Europe Conference & Exhibition, 1-6, 2007 | 13 | 2007 |
| Stimulating curiosity and the ability to formulate technical questions in an electric circuits course using the question formulation technique (QFT) HJ LeBlanc, K Nepal, GS Mowry 2017 IEEE Frontiers in Education Conference (FIE), 1-6, 2017 | 12 | 2017 |
| Using Platform FPGAs for Fault Emulation and Test-set Generation to Detect Stuck-at Faults. C Dunbar, K Nepal J. Comput. 6 (11), 2335-2344, 2011 | 12 | 2011 |
| Compacting test vector sets via strategic use of implications N Alves, J Dworak, I Bahar, K Nepal Computer-Aided Design-Digest of Technical Papers, 2009. ICCAD 2009. IEEE/ACM …, 2009 | 10 | 2009 |
| Low-power FPGA routing switches using adaptive body biasing technique GV Leming, K Nepal 2009 52nd IEEE International Midwest Symposium on Circuits and Systems, 447-450, 2009 | 10 | 2009 |
| Combinational hardware Trojan detection using logic implications N Cornell, K Nepal 2017 IEEE 60th International Midwest Symposium on Circuits and Systems …, 2017 | 9 | 2017 |
| Detecting a trojan die in 3D stacked integrated circuits S Alhelaly, J Dworak, T Manikas, P Gui, K Nepal, AL Crouch 2017 IEEE North Atlantic Test Workshop (NATW), 1-6, 2017 | 9 | 2017 |
Theodore ManikasSouthern Methodist UniversityVerified email at lyle.smu.edu
