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Matthew Areno
Matthew Areno
Security Architect at Intel
Verified email at intel.com
Title
Cited by
Cited by
Year
Securing trusted execution environments with puf generated secret keys
M Areno, J Plusquellic
2012 IEEE 11th International Conference on Trust, Security and Privacy in …, 2012
322012
Firmware security interface for field programmable gate arrays
MC Areno, J Hoffman, WT Jennings
US Patent 9,940,483, 2018
252018
An autonomous, self-authenticating, and self-contained secure boot process for field-programmable gate arrays
D Owen Jr, D Heeger, C Chan, W Che, F Saqib, M Areno, J Plusquellic
Cryptography 2 (3), 15, 2018
182018
Controlling security state of commercial off the shelf (COTS) system
MC Areno, JC Hoffman
US Patent 11,347,861, 2022
172022
Apparatus, system and method for providing cryptographic key information with physically unclonable function circuitry
M Areno
US Patent 9,208,355, 2015
172015
Self-authenticating secure boot for FPGAs
G Pocklassery, W Che, F Saqib, M Areno, J Plusquellic
2018 IEEE International Symposium on Hardware Oriented Security and Trust …, 2018
142018
ASIC implementation of a hardware‐embedded physical unclonable function
F Saqib, M Areno, J Aarestad, J Plusquellic
IET Computers & Digital Techniques 8 (6), 288-299, 2014
142014
A reconfigurable load balancing architecture for molecular dynamics
J Phillips, M Areno, C Rogers, A Dasu, B Eames
2007 IEEE International Parallel and Distributed Processing Symposium, 1-6, 2007
112007
An fpga-based dynamic load-balancing processor architecture for solving n-body problems
J Phillips, M Areno, B Eames, A Dasu
Proceedings of the 10th Annual High Performance Embedded Computing Workshop, 2006
82006
Correlation-based robust authentication (Cobra) using helper data only
J Plusquellic, M Areno
Cryptography 2 (3), 21, 2018
42018
Correlation-based robust authentication technique using helper data only
J Plusquellic, M Areno
US Patent 11,411,751, 2022
32022
A force-directed scheduling based architecture generation algorithm and design tool for fpgas
M Areno, B Eames, J Templin
Journal of Systems Architecture 56 (2-3), 124-135, 2010
32010
Automated constraint-based hardware architecture generation for reconfigurable computing systems
MC Areno
Utah State University, 2007
32007
Secure Mobile Association and Data Protection with Enhanced Cryptographic Engines.
M Areno
Sandia National Lab.(SNL-NM), Albuquerque, NM (United States), 2013
22013
Strengthening embedded system security with PUF enhanced cryptographic engines
MC Areno
The University of New Mexico, 2013
22013
Secure mobile authentication and device association with enhanced cryptographic engines
M Areno, J Plusquellic
2013 International Conference on Privacy and Security in Mobile Systems …, 2013
12013
Reprogrammable processing device root key architecture
M Areno
US Patent App. 18/312,838, 2023
2023
System and method for booting processors with encrypted boot image
MC Areno, JR Coleman, D Adams
US Patent 11,423,150, 2022
2022
An Autonomous, Self-Authenticating and Self-Contained Secure Boot Process for FPGAs
D Heeger, W Che, F Saqib, M Areno, J Plusquellic
Sandia National Lab.(SNL-NM), Albuquerque, NM (United States), 2022
2022
Cross-domain solution using network-connected hardware root-of-trust device
MC Areno, RA Nelson
US Patent 11,178,159, 2021
2021
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