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Josep M. Codina
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Year
Graph-partitioning based instruction scheduling for clustered processors
A Aleta, JM Codina, J Sánchez, A González
Proceedings. 34th ACM/IEEE International Symposium on Microarchitecture …, 2001
902001
Register checkpointing mechanism for multithreading
P Lopez, C Madriles, A Martinez, R Martinez, JM Codina, EG Codina, ...
US Patent App. 12/420,762, 2010
882010
Register Checkpointing Mechanism For Multithreading
AG Pedro Lopez, Carlos Madriles, Alejandro Martinez, Raul Martinez, Josep M ...
US Patent 20,100,262,812, 2010
88*2010
A comparative study of modulo scheduling techniques
JM Codina, J Llosa, A González
Proceedings of the 16th international conference on Supercomputing, 97-106, 2002
862002
A unified modulo scheduling and register allocation technique for clustered processors
JM Codina, J Sánchez, A González
Proceedings 2001 International Conference on Parallel Architectures and …, 2001
762001
Systems, methods, and apparatuses to decompose a sequential program into multiple threads, execute said threads, and reconstruct the sequential execution
F Latorre, JM Codina, EG Codina, P Lopez, C Madriles, AM Vincente, ...
US Patent 8,909,902, 2014
632014
Substrate pads with reduced impedance mismatch and methods to fabricate substrate pads
TK Chin, W Landucci
US Patent 6,765,298, 2004
56*2004
Boosting single-thread performance in multi-core systems through fine-grain multi-threading
C Madriles, P López, JM Codina, E Gibert, F Latorre, A Martínez, ...
ACM SIGARCH Computer Architecture News 37 (3), 474-483, 2009
542009
Instruction replication for clustered microarchitectures
A Aleta, JM Codina, A Gonzalez, D Kaeli
Proceedings. 36th Annual IEEE/ACM International Symposium on …, 2003
312003
Exploiting pseudo-schedules to guide data dependence graph partitioning
A Aleta, JM Codina, J Sánchez, A González, D Kaeli
Proceedings. International Conference on Parallel Architectures and …, 2002
312002
Access of register files of other threads using synchronization
E Gibert, JM Codina, F Latorre, JA Piñeiro, P López, A González
US Patent 8,261,046, 2012
292012
Cache sharing based thread control
A Gonzalez, JM Codina, P Lopez, F Latorre, JA Pineiro, E Gibert, J Abella, ...
US Patent 7,895,415, 2011
272011
Anaphase: A fine-grain thread decomposition scheme for speculative multithreading
C Madriles, P Lopez, JM Codina, E Gibert, F Latorre, A Martinez, ...
2009 18th International Conference on Parallel Architectures and Compilation …, 2009
262009
Adaptive antenna reception apparatus
T Shibata
US Patent 7,103,120, 2006
262006
AGAMOS: A graph-based approach to modulo scheduling for clustered microarchitectures
A Aleta, JM Codina, J Sánchez, A González, D Kaeli
IEEE Transactions on computers 58 (6), 770-783, 2009
242009
Heterogeneous clustered VLIW microarchitectures
À Aletà, JM Codina, A González, D Kaeli
International Symposium on Code Generation and Optimization (CGO'07), 354-366, 2007
222007
Achieving coherence between dynamically optimized code and original code
F Latorre, G Magklis, E Gibert, JM Codina, A González
US Patent 8,190,652, 2012
192012
Path profiling using hardware and software combination
C Madriles, JM Codina, CE Kotselidis, AM Vicente
US Patent App. 13/994,193, 2014
172014
Softhv: A hw/sw co-designed processor with horizontal and vertical fusion
A Deb, JM Codina, A González
Proceedings of the 8th ACM international Conference on Computing Frontiers, 1-10, 2011
172011
Merging level cache and data cache units having indicator bits related to speculative execution
F Latorre, JM Codina, EG Codina, P Lopez, C Madriles, AM Vincente, ...
US Patent 10,621,092, 2020
162020
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