| 2D materials: roadmap to CMOS integration C Huyghebaert, T Schram, Q Smets, TK Agarwal, D Verreck, S Brems, ... 2018 IEEE International Electron Devices Meeting (IEDM), 22.1. 1-22.1. 4, 2018 | 95 | 2018 |
| Tunneling Transistors Based on MoS2/MoTe2 Van der Waals Heterostructures Y Balaji, Q Smets, CJL De La Rosa, AKA Lu, D Chiappe, T Agarwal, ... IEEE Journal of the Electron Devices Society 6, 1048-1055, 2018 | 46 | 2018 |
| Benchmarking of MoS2 FETs With Multigate Si-FET Options for 5 nm and Beyond T Agarwal, D Yakimets, P Raghavan, I Radu, A Thean, M Heyns, ... IEEE Transactions on Electron Devices 62 (12), 4051-4056, 2015 | 36 | 2015 |
| Bilayer graphene tunneling FET for sub-0.2 V digital CMOS logic applications TK Agarwal, A Nourbakhsh, P Raghavan, I Radu, S De Gendt, M Heyns, ... IEEE Electron Device Letters 35 (12), 1308-1310, 2014 | 22 | 2014 |
| Material-device-circuit co-optimization of 2D material based FETs for ultra-scaled technology nodes TK Agarwal, B Soree, I Radu, P Raghavan, G Iannaccone, G Fiori, ... Scientific reports 7 (1), 5016, 2017 | 21 | 2017 |
| Scaling trends and performance evaluation of 2-dimensional polarity-controllable FETs GV Resta, T Agarwal, D Lin, IP Radu, F Catthoor, PE Gaillardon, ... Scientific reports 7 (1), 45556, 2017 | 21 | 2017 |
| Comparison of short-channel effects in monolayer MoS2 based junctionless and inversion-mode field-effect transistors T Agarwal, B Sorée, I Radu, P Raghavan, G Fiori, G Iannaccone, A Thean, ... Applied Physics Letters 108 (2), 2016 | 21 | 2016 |
| Benchmarking of monolithic 3D integrated MX2 FETs with Si FinFETs T Agarwal, A Szabo, MG Bardon, B Sorée, I Radu, P Raghavan, M Luisier, ... 2017 IEEE international electron devices meeting (IEDM), 5.7. 1-5.7. 4, 2017 | 19 | 2017 |
| Bilayer graphene tunneling field effect transistor A Nourbakhsh, B Soree, M Heyns, TK Agarwal US Patent 9,293,536, 2016 | 18 | 2016 |
| Performance Comparison of Static CMOS and MCML gates in sub-threshold region of operation for 32nm CMOS Technology TK Agarwal, A Sawhney, AK Kureshi, M Hasan 2008 International Conference on Computer and Communication Engineering, 284-287, 2008 | 14 | 2008 |
| Heterostructure at CMOS source/drain: Contributor or alleviator to the high access resistance problem? H Yu, M Schaekers, E Rosseel, JL Everaert, P Eyben, T Chiarella, ... 2016 IEEE International Electron Devices Meeting (IEDM), 25.1. 1-25.1. 4, 2016 | 13 | 2016 |
| 2018 IEEE Int. Electron Devices Meeting (IEDM) C Huyghebaert, T Schram, Q Smets, TK Agarwal, D Verreck, S Brems, ... IEEE, 2018 | 12 | 2018 |
| Effect of material parameters on two-dimensional materials based TFETs: An energy-delay perspective T Agarwal, I Radu, P Raghavan, G Fiori, A Thean, M Heyns, W Dehaene 2016 46th European Solid-State Device Research Conference (ESSDERC), 47-50, 2016 | 12 | 2016 |
| Mohd TK Agarwal, A Sawhney, AK Kureshi Hasan" Performance Comparison of Static CMOS and CML gates in sub-threshold …, 2008 | 11 | 2008 |
| A MOS capacitor model for ultra-thin 2D semiconductors: the impact of interface defects and channel resistance A Gaur, T Agarwal, I Asselberghs, I Radu, M Heyns, D Lin 2D Materials 7 (3), 035018, 2020 | 10 | 2020 |
| Design optimization of gate-all-around vertical nanowire transistors for future memory applications TK Agarwal, O Badami, S Ganguly, S Mahapatra, D Saha 2013 IEEE International Conference of Electron Devices and Solid-state …, 2013 | 10 | 2013 |
| Ion Migration in Monolayer Memristors S Papadopoulos, T Agarwal, A Jain, T Taniguchi, K Watanabe, M Luisier, ... Physical Review Applied 18 (1), 014018, 2022 | 7 | 2022 |
| Origin of the performances degradation of two-dimensional-based metal-oxide-semiconductor field effect transistors in the sub-10 nm regime: A first-principles study AKA Lu, G Pourtois, T Agarwal, A Afzalian, IP Radu, M Houssa Applied Physics Letters 108 (4), 2016 | 7 | 2016 |
| Compact modeling of partially depleted silicon-on-insulator drain-extended MOSFET (DEMOSFET) including high-voltage and floating-body effects TK Agarwal, AR Trivedi, V Subramanian, MJ Kumar IEEE transactions on electron devices 58 (10), 3485-3493, 2011 | 7 | 2011 |
| Performance comparison of CNFET and CMOS based full adders at the 32 nm technology node T Agarwal, A Sawhney, AK Kureshi, M Hasan Proceedings of VLSI Design and Test Symposium (VDAT), 49-57, 2008 | 7 | 2008 |
Iuliana RaduTSMCVerified email at tsmc.com
