| A 12-bit, 2.5-bit/Phase Column-Parallel Cyclic ADC A Kaur, D Mishra, M Sarkar IEEE Transactions on Very Large Scale Integration (VLSI) Systems 27 (1), 248-252, 2018 | 17 | 2018 |
| Content Driven on-chip Compression and Time Efficient Reconstruction for Image Sensor Applications A Kaur, D Mishra, S Jain, M Sarkar IEEE Sensors Journal, 2018 | 12 | 2018 |
| A low power low latency comparator for ramp ADC in CMOS imagers A Kaur, M Sarkar 2016 IEEE International Symposium on Circuits and Systems (ISCAS), 1466-1469, 2016 | 11 | 2016 |
| A 12-bit, 2.5-bit/cycle, 1 MS/s two-stage cyclic ADC, for high-speed CMOS image sensors A Kaur, D Mishra, M Sarkar 2018 IEEE International Symposium on Circuits and Systems (ISCAS), 1-5, 2018 | 10 | 2018 |
| On-Array Compressive Acquisition in CMOS Image Sensors Using Accumulated Spatial Gradients A Kaur, D Mishra, KM Amogh, M Sarkar IEEE Transactions on Circuits and Systems for Video Technology 31 (2), 523-532, 2020 | 9 | 2020 |
| An on-Chip Interpolation Based Readout Scheme for Low-Power, High-Speed CMOS Image Sensors A Kaur, D Mishra, M Sarkar IEEE SENSORS, 2018, 2018 | 6 | 2018 |
| A super-pixel based on-chip image compression for high speed CMOS image sensors D Mishra, A Kaur, M Sarkar 2017 International Conference on Electron Devices and Solid-State Circuits …, 2017 | 6 | 2017 |
| A power efficient image sensor readout with on-chip δ-interpolation using reconfigurable ADC A Kaur, D Mishra, M Sarkar IEEE Sensors Journal, 2019 | 5 | 2019 |
| A low kickback noise and low power dynamic comparator B Satapathy, A Kaur 2021 IEEE International Midwest Symposium on Circuits and Systems (MWSCAS …, 2021 | 4 | 2021 |
| A High speed, Low Energy Comparator Based on Current Recycling Approach B Satapathy, A Kaur IEEE International Symposium on Circuits and Systems (ISCAS), 2021 | 3 | 2021 |
| On-chip Pixel Reconstruction using Simple CNN for Sparsely Read CMOS Image Sensor W Kisku, A Kaur, D Mishra 2021 IEEE 3rd International Conference on Artificial Intelligence Circuits …, 2021 | 2 | 2021 |
| A reconfigurable Cyclic ADC for Biomedical Applications A Kaur, D Mishra IEEE Biomedical Circuits and Systems Conference, 2019 | 2 | 2019 |
| A 1.2 V, 33 ppm/° C, 40 nW, regeneration based BGR circuit for nanowatt CMOS LSIs A Shrivastava, A Kaur, M Sarkar 2017 International SoC Design Conference (ISOCC), 111-112, 2017 | 2 | 2017 |
| An Intelligent System with Reduced Readout Power and Lightweight CNN for Vision Applications W Kisku, A Kaur, D Mishra IEEE Transactions on Circuits and Systems for Video Technology, 2023 | 1 | 2023 |
| A CMOS Image Sensor with column-parallel cyclic-SAR ADC A Kaur, Karthik, M Sarkar IEEE International Symposium on Circuits and Systems (ISCAS), 2020 | 1 | 2020 |
| An Energy-efficient and High-speed Dynamic Comparator for Low-noise Applications B Satapathy, A Kaur Circuits, Systems, and Signal Processing 42 (9), 5108-5120, 2023 | | 2023 |
| A Single Capacitor-Based Offset Reduction Technique for Energy-Efficient Dynamic Comparators B Satapathy, A Kaur 2023 IEEE International Symposium on Circuits and Systems (ISCAS), 1-5, 2023 | | 2023 |
| AI driven Wide Dynamic Range CMOS Image Sensor W Kisku, M Bhushan, A Kaur, D Mishra 2022 IEEE 4th International Conference on Artificial Intelligence Circuits …, 2022 | | 2022 |
| An input folding high speed cyclic ADC for column-parallel readout in CMOS image sensors A Kaur, M Sarkar 2022 IEEE International Symposium on Circuits and Systems (ISCAS), 910-914, 2022 | | 2022 |
| A Multiplying Digital to Analog Converter Insensitive to Component Mismatch A Kaur 2022 IEEE International Symposium on Circuits and Systems (ISCAS), 1440-1444, 2022 | | 2022 |
