| Devices with adjustable dual-polarity trigger-and holding-voltage/current for high level of electrostatic discharge protection in sub-micron mixed signal CMOS/BiCMOS integrated … JA Salcedo, JJ Liou, JC Bernier, DK Whitney US Patent 7,566,914, 2009 | 119 | 2009 |
| Bi-directional blocking voltage protection devices and methods of forming the same JA Salcedo, M Lynch, B Moane US Patent 8,680,620, 2014 | 110 | 2014 |
| On-chip structure for electrostatic discharge (ESD) protection JA Salcedo, JJ Liou, JC Bernier, DK Whitney Jr US Patent 7,202,114, 2007 | 106 | 2007 |
| On-Chip structure for electrostatic discharge (ESD) protection JA Salcedo, JJ Liou, JC Bernier, DK Whitney Jr US Patent 7,601,991, 2009 | 86 | 2009 |
| Junction-isolated blocking voltage devices with integrated protection structures and methods of forming the same DJ Clarke, JA Salcedo, BB Moane, J Luo, S Murnane, KK Heffernan, ... US Patent 8,796,729, 2014 | 80 | 2014 |
| Apparatus and method for protecting electronic circuits JA Salcedo, D Casey, G McCorkell US Patent 8,368,116, 2013 | 73 | 2013 |
| Electrostatic discharge protection device for digital circuits and for applications with input/output bipolar voltage much higher than the core circuit power supply JA Salcedo, JJ Liou, JC Bernier, DK Whitney US Patent 7,285,828, 2007 | 70 | 2007 |
| Apparatus and method for electronic circuit protection JA Salcedo US Patent 8,553,380, 2013 | 68 | 2013 |
| Electrostatic discharge protection device for digital circuits and for applications with input/output bipolar voltage much higher than the core circuit power supply JA Salcedo, JJ Liou, JC Bernier, DK Whitney US Patent 7,479,414, 2009 | 68 | 2009 |
| Apparatus and method for transient electrical overstress protection JA Salcedo, K Sweetland US Patent 8,466,489, 2013 | 67 | 2013 |
| Apparatus and method for integrated circuit protection JA Salcedo, P Cheung US Patent 8,665,571, 2014 | 66 | 2014 |
| New simple procedure to determine the threshold voltage of MOSFETs FJG Sánchez, A Ortiz-Conde, G De Mercato, JA Salcedo, JJ Liou, Y Yue Solid-State Electronics 44 (4), 673-675, 2000 | 63 | 2000 |
| Apparatus and method for protection of precision mixed-signal electronic circuits JA Salcedo, S Parthasarathy US Patent 8,946,822, 2015 | 62 | 2015 |
| Bond pad with integrated transient over-voltage protection J Salcedo, A Righter US Patent 8,222,698, 2012 | 62 | 2012 |
| Transient over-voltage clamp J Salcedo, A Righter US Patent 8,044,457, 2011 | 62 | 2011 |
| Apparatuses for communication systems transceiver interfaces JA Salcedo, DJ Clarke US Patent 9,831,233, 2017 | 61 | 2017 |
| Apparatus and method for protection of electronic circuits operating under high stress conditions JA Salcedo, DH Whitney US Patent 8,592,860, 2013 | 61 | 2013 |
| Method and apparatus for protection and high voltage isolation of low voltage communication interface terminals JA Salcedo US Patent 8,637,899, 2014 | 60 | 2014 |
| Protection systems for integrated circuits and methods of forming the same JA Salcedo, DJ Clarke, GP Cosgrave, Y Huang US Patent 8,947,841, 2015 | 59 | 2015 |
| Apparatus and method for electronic systems reliability JA Salcedo, D Casey, G McCorkell US Patent 8,432,651, 2013 | 59 | 2013 |
