| Accurate robustness assessment of hdl models through iterative statistical fault injection I Tuzov, D de Andrés, JC Ruiz 2018 14th European Dependable Computing Conference (EDCC), 1-8, 2018 | 15 | 2018 |
| DAVOS: EDA toolkit for dependability assessment, verification, optimisation and selection of hardware models I Tuzov, D de Andrés, JC Ruiz 2018 48th Annual IEEE/IFIP International Conference on Dependable Systems …, 2018 | 13 | 2018 |
| Speeding-up simulation-based fault injection of complex hdl models I Tuzov, JC Ruiz, D De Andrés, P Gil 2016 Seventh Latin-American Symposium on Dependable Computing (LADC), 51-60, 2016 | 12 | 2016 |
| Tuning synthesis flags to optimize implementation goals: Performance and robustness of the LEON3 processor as a case study I Tuzov, D de Andrés, JC Ruiz Journal of Parallel and Distributed Computing 112, 84-96, 2018 | 10 | 2018 |
| Анимация и видео в научной публикации ММ Горбунов-Посадов, ДС Ролдугин, МИ Слепенков, ИВ Тузов Препринты Института прикладной математики им. МВ Келдыша РАН, 104-32, 2014 | 10 | 2014 |
| Dependability-aware design space exploration for optimal synthesis parameters tuning I Tuzov, D de Andrés, JC Ruiz 2017 47th Annual IEEE/IFIP International Conference on Dependable Systems …, 2017 | 8 | 2017 |
| Accurately simulating the effects of faults in vhdl models described at the implementation-level I Tuzov, JC Ruiz, D de Andrés 2017 13th European Dependable Computing Conference (EDCC), 10-17, 2017 | 6 | 2017 |
| Improving the robustness of redundant execution with register file randomization I Tuzov, P Andreu, L Medina, T Picornell, A Robles, P Lopez, J Flich, ... 2021 IEEE/ACM International Conference On Computer Aided Design (ICCAD), 1-9, 2021 | 4 | 2021 |
| Robustness-aware design space exploration through iterative refinement of d-optimal designs I Tuzov, D de Andrés, JC Ruiz 2019 15th European Dependable Computing Conference (EDCC), 23-30, 2019 | 3 | 2019 |
| A survey of recent developments in testability, safety and security of risc-v processors J Anders, P Andreu, B Becker, S Becker, R Cantoro, NI Deligiannis, ... 2023 IEEE European Test Symposium (ETS), 1-10, 2023 | 2 | 2023 |
| Reversing FPGA architectures for speeding up fault injection: does it pay? I Tuzov, D de Andrés, JC Ruiz 2022 18th European Dependable Computing Conference (EDCC), 81-88, 2022 | 2 | 2022 |
| Dependability-driven strategies to improve the design and verification of safety-critical HDL-based embedded systems I Tuzov Universitat Politècnica de València, 2020 | 2 | 2020 |
| BAFFI: a bit-accurate fault injector for improved dependability assessment of FPGA prototypes I Tuzov, D de Andrés, JC Ruiz, C Hernández 2023 Design, Automation & Test in Europe Conference & Exhibition (DATE), 1-6, 2023 | 1 | 2023 |
| Using Look Up Table Content as Signatures to Identify IP Cores in Modern FPGAs A Asghar, AK Robillard, I Tuzov, A Becher, D Ziener International Conference on Architecture of Computing Systems, 132-147, 2022 | | 2022 |
| Improving Robustness-Aware Design Space Exploration for FPGA-Based Systems I Tuzov, D de Andrés, JC Ruiz 2020 16th European Dependable Computing Conference (EDCC), 1-8, 2020 | | 2020 |
| Simulating the effects of logic faults in implementation-level VITAL-compliant models I Tuzov, D de Andrés, JC Ruiz Computing 101 (2), 77-96, 2019 | | 2019 |
| Speeding-up robustness assessment of HDL models through profiling and multi-level fault injection I Tuzov, D de Andrés, JC Ruiz 2018 Eighth Latin-American Symposium on Dependable Computing (LADC), 97-106, 2018 | | 2018 |
| EDCC 2019 M Torquato, M Vieira, T Fabarisov, K Janschek, H Schirmeier, ... | | |
| EDCC 2018 I Tuzov, D de Andrés, JR Campos, M Vieira, E Costa, L Coppolino, ... | | |
