| Implementation of Scan Logic and Pattern Generation for RTL Design R Madhura, MJ Shantiprasad New Trends in Computational Vision and Bio-inspired Computing: Selected …, 2020 | 1 | 2020 |
| Semiconductor Fault Diagnosis Using Deep Learning-Based Domain Adaption KH Krishnappa, MM Hiremath, R Manasa, R Madhura, N Holla, ... International Journal of Intelligent Systems and Applications in Engineering …, 2024 | | 2024 |
| UVM Methodology for ARINC 429 Transceiver in Loop Back Mode R Madhura, KH Krishnappa, R Shashidhar, G Shwetha, KP Yashaswini, ... 2023 3rd International Conference on Mobile Networks and Wireless …, 2023 | | 2023 |
| EEG Data Analysis for Stress Detection using K-Nearest Neighbor R Shashidhar, P Kadakol, D Sreeniketh, P Patil, KH Krishnappa, ... 2023 International Conference on Integrated Intelligence and Communication …, 2023 | | 2023 |
| Slack Time Analysis for APB Timer Using Genus Synthesis Tool R Madhura, KH Krishnappa, R Manasa, KP Yashaswini International Conference on ICT for Sustainable Development, 207-217, 2023 | | 2023 |
| ATSPEED SCAN TESTING FOR RTL DESIGN IN LOWER TECHNOLOGY NODE Madhura R | | 2022 |
| FPGA Based Efficient LFSR Architecture for Verification Using Optimized BIST Technique SPMJ Madhura.R International Journal of Emerging Trends in Engineering Research 10 (8), 7, 2020 | | 2020 |
| FPGA Implementation of Optimized BIST Architecture for Testing of Logic Circuits M R International Journal of VLSI & Signal Processing 7 (Issue 02), 7, 2020 | | 2020 |
| FPGA Implementation of Optimized BIST Architecture for Testing of Logic Circuits R Ramya, R Madhura | | |
| 3rd International Conference on Mobile Networks and Wireless Communications (ICMNWC J Aqui, M Hosein, M Indoonundon, TP Fowdur, DA Milovanovic, ... System 24, 207, 0 | | |
| Popular Case Studies of Various VLSI Test Scan Architectures B DSCE, SP MJ, B KSIT | | |
| Comprehensive Study of Popular VLSI Test Scan Architecture SPMJ Madhura.R | | |
