| Machine learned machines: Adaptive co-optimization of caches, cores, and on-chip network R Jain, PR Panda, S Subramoney 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE), 253-256, 2016 | 26 | 2016 |
| Defect-aware design paradigm for reconfigurable architectures R Jain, A Mukherjee, K Paul IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and …, 2006 | 25 | 2006 |
| An efficient pipelined VLSI architecture for lifting-based 2d-discrete wavelet transform R Jain, PR Panda 2007 IEEE International Symposium on Circuits and Systems, 1377-1380, 2007 | 21 | 2007 |
| Cooperative multi-agent reinforcement learning-based co-optimization of cores, caches, and on-chip network R Jain, PR Panda, S Subramoney ACM Transactions on Architecture and Code Optimization (TACO) 14 (4), 1-25, 2017 | 20 | 2017 |
| A Coordinated Multi-Agent Reinforcement Learning Approach to Multi-Level Cache Co-partitioning R Jain, PR Panda, S Subramoney 2017, Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017 | 14 | 2017 |
| Memory architecture exploration for power-efficient 2d-discrete wavelet transform R Jain, PR Panda 20th International Conference on VLSI Design held jointly with 6th …, 2007 | 7 | 2007 |
| A power efficient architecture for 2-d discrete wavelet transform R Jain, PR Panda 10th IEEE Symposium on VLSI Design and Testing, Goa, 2006 | 2 | 2006 |
Preeti Ranjan PandaProfessor in Computer Science and Engineering, Indian Institute of Technology DelhiVerified email at cse.iitd.ac.in
