| Configurable and scalable high throughput turbo decoder architecture for multiple 4G wireless standards Y Sun, Y Zhu, M Goel, JR Cavallaro 2008 International Conference on Application-Specific Systems, Architectures …, 2008 | 77 | 2008 |
| Methods and apparatus to measure and analyze vibration signatures LW Estevez, Y Zhu, SM Patole US Patent 10,416,306, 2019 | 41 | 2019 |
| Design and analysis of LDPC decoders for software defined radio S Seo, T Mudge, Y Zhu, C Chakrabarti 2007 IEEE Workshop on Signal Processing Systems, 210-215, 2007 | 41 | 2007 |
| Forward error correction decoding for WiMAX and 3GPP LTE modems SJ Lee, M Goel, Y Zhu, JF Ren, Y Sun 2008 42nd Asilomar Conference on Signals, Systems and Computers, 1143-1147, 2008 | 27 | 2008 |
| Memory Access in Low-Density Parity Check Decoders S Lingam, Y Zhu, A Ahmed, S Begum US Patent App. 12/436,756, 2009 | 23 | 2009 |
| Architecture-aware LDPC code design for multiprocessor software defined radio systems Y Zhu, C Chakrabarti IEEE transactions on signal processing 57 (9), 3679-3692, 2009 | 13 | 2009 |
| High-speed add-compare-select (ACS) circuit S Lee, Y Zhu, M Goel US Patent 8,205,145, 2012 | 12 | 2012 |
| CRC-based forward error correction circuitry and method JF Ren, M Goel, Y Zhu US Patent 9,543,981, 2017 | 10 | 2017 |
| Architecture-aware LDPC code design for software defined radio Y Zhu, C Chakrabarti 2006 IEEE Workshop on Signal Processing Systems Design and Implementation …, 2006 | 8 | 2006 |
| Scalable decoder architecture for low density parity check codes Y Sun, Y Zhu, M Goel US Patent 8,307,255, 2012 | 7 | 2012 |
| Memory sub-banking scheme for high throughput turbo decoder M Tiwari, Y Zhu, C Chakrabarti 2004 IEEE International Conference on Acoustics, Speech, and Signal …, 2004 | 6 | 2004 |
| Configurable and Scalable Turbo Decoder for 4G Wireless receivers Y Sun, JR Cavallaro, Y Zhu, M Goel Fourth-Generation Wireless Networks: Applications and Innovations, 622-643, 2010 | 5 | 2010 |
| A reduced-complexity, scalable implementation of low density parity check (LDPC) decoder Y Zhu, Y Chen, D Hocevar, M Goel 2006 IEEE Workshop on Signal Processing Systems Design and Implementation, 83-88, 2006 | 5 | 2006 |
| Memory sub-banking scheme for high throughput MAP-based SISO decoders M Tiwari, Y Zhu, C Chakrabarti IEEE transactions on very large scale integration (VLSI) systems 13 (4), 494-498, 2005 | 5 | 2005 |
| Error correction code management of write-once memory codes S Zhang, Y Zhu, C Bittlestone, S Ramaswamy US Patent 9,772,899, 2017 | 4 | 2017 |
| Dual-mode error-correction code/write-once memory codec S Zhang, Y Zhu, C Bittlestone, S Ramaswamy US Patent 9,690,517, 2017 | 4 | 2017 |
| Scalable folded decoder architecture for low density parity check codes Y Zhu, M Goel US Patent 8,307,269, 2012 | 4 | 2012 |
| Aggregated circulant matrix based LDPC codes Y Zhu, C Chakrabarti 2006 IEEE International Conference on Acoustics Speech and Signal Processing …, 2006 | 4 | 2006 |
| Methods and apparatus to determine and apply polarity-based error correction code M Goel, Y Zhu US Patent 10,523,240, 2019 | 3 | 2019 |
| Parity check decoder architecture Y Zhu, Y Chen, DE Hocevar, M Goel US Patent 7,945,838, 2011 | 3 | 2011 |
