| A 167-processor computational platform in 65 nm CMOS DN Truong, WH Cheng, T Mohsenin, Z Yu, AT Jacobson, G Landge, ... IEEE Journal of Solid-State Circuits 44 (4), 1130-1144, 2009 | 314 | 2009 |
| A 167-processor 65 nm computational platform with per-processor dynamic supply voltage and dynamic clock frequency scaling D Truong, W Cheng, T Mohsenin, Z Yu, T Jacobson, G Landge, ... 2008 IEEE Symposium on VLSI Circuits, 22-23, 2008 | 90 | 2008 |
| Toward more accurate scaling estimates of cmos circuits from 180 nm to 22 nm A Stillmaker, Z Xiao, B Baas VLSI Computation Lab, ECE Department, University of California, Davis, Tech …, 2011 | 55 | 2011 |
| Rethinking Network Pruning--under the Pre-train and Fine-tune Paradigm D Xu, IEH Yen, J Zhao, Z Xiao arXiv preprint arXiv:2104.08682, 2021 | 42 | 2021 |
| Embedded software optimization for MP3 decoder implemented on RISC core Y Yao, Q Yao, P Liu, Z Xiao IEEE Transactions on Consumer Electronics 50 (4), 1244-1249, 2004 | 36 | 2004 |
| A high-performance parallel CAVLC encoder on a fine-grained many-core system Z Xiao, B Baas 2008 IEEE International Conference on Computer Design, 248-254, 2008 | 32 | 2008 |
| A fine-grained parallel implementation of a H. 264/AVC encoder on a 167-processor computational platform Z Xiao, S Le, B Baas 2011 Conference Record of the Forty Fifth Asilomar Conference on Signals …, 2011 | 30 | 2011 |
| A 1080p H. 264/AVC baseline residual encoder for a fine-grained many-core system Z Xiao, BM Baas IEEE transactions on circuits and systems for video technology 21 (7), 890-902, 2011 | 28 | 2011 |
| Optimizing pipeline for a RISC processor with multimedia extension ISA Z Xiao, P Liu, Y Yao, Q Yao Journal of Zhejiang University-Science A 7 (2), 269-274, 2006 | 18 | 2006 |
| MediaSOC: A system-on-chip architecture for multimedia application P Liu, W Wang, Z Xiao, L Lai, Z Teng, G Yu, Y Yao, K Chen, Y Zhang, ... Proceedings of 2005 IEEE International Workshop on VLSI Design and Video …, 2005 | 14 | 2005 |
| Method and system for hierarchical weight-sparse convolution processing Z Xiao, E Yan, W Wang, Y Lu US Patent 10,970,619, 2021 | 8 | 2021 |
| A 167-processor computational array for highly-efficient DSP and embedded application processing D Truong, W Cheng, T Mohsenin, Z Yu, T Jacobson, G Landge, ... 2008 IEEE Hot Chips 20 Symposium (HCS), 1-27, 2008 | 8 | 2008 |
| 微处理器功能验证程序生成 姚英彪， 刘鹏， 姚庆栋， 肖志斌 计算机辅助设计与图形学学报 18 (10), 1484-1490, 2006 | 6 | 2006 |
| A hexagonal processor and interconnect topology for many-core architecture with dense on-chip networks Z Xiao, B Baas VLSI-SoC: From Algorithms to Circuits and System-on-Chip Design: 20th IFIP …, 2013 | 5 | 2013 |
| A hexagonal shaped processor and interconnect topology for tightly-tiled many-core architecture Z Xiao, B Baas 2012 IEEE/IFIP 20th International Conference on VLSI and System-on-Chip …, 2012 | 5 | 2012 |
| Method and system for balanced-weight sparse convolution processing Z Xiao, E Yan, W Wang, Y Lu US Patent 11,113,601, 2021 | 3 | 2021 |
| Processor tile Shapes and interconnect topologies for dense On-chip networks Z Xiao, BM Baas IEEE Transactions on Very Large Scale Integration (VLSI) Systems 22 (6 …, 2013 | 3 | 2013 |
| Energy-efficient string search architectures on a fine-grained many-core platform EO Adeagbo, BM Baas, Z Xiao, B Baas, A Stillmaker, L Stillmaker, B Baas, ... Technology and Talent for the 21st Century (TECHCON 2015), 2015 | 2 | 2015 |
| Hardware and applications of asap: An asynchronous array of simple processors D Truong, W Cheng, T Mohsenin, ZYT Jacobson, G Landge, ... HotChips 2008, 2008 | 2 | 2008 |
| Adaptive tensor compute kernel for sparse neural network X Zhang, E Yan, Z Xiao US Patent App. 17/673,490, 2023 | 1 | 2023 |
Dean TruongResearch Assistant, University of California, DavisVerified email at ucdavis.edu
