| Software-based self-test generation for microprocessors with high-level decision diagrams R Ubar, A Tsertov, A Jasnetski, M Brik 2014 15th Latin American Test Workshop-LATW, 1-6, 2014 | 11 | 2014 |
| Multi-level fault simulation of digital systems on decision diagrams R Ubar, J Raik, E Ivask, M Brik Proceedings First IEEE International Workshop on Electronic Design, Test and …, 2002 | 10 | 2002 |
| Software-based self-test generation for microprocessors with high-level decision diagrams A Jasnetski, R Ubar, A Tsertov, M Brik Proceedings of the Estonian Academy of Sciences 63 (1), 48, 2014 | 9 | 2014 |
| Multi-level test generation and fault diagnosis for finite state machines R Ubar, M Brik European Dependable Computing Conference, 264-281, 1996 | 9 | 1996 |
| A benchmark suite for evaluating the efficiency of test tools H Kruus, R Ubar, P Ellervee, M Gorev, V Pesonen, S Devadze, E Orasson, ... 2012 13th Biennial Baltic Electronics Conference, 85-88, 2012 | 3 | 2012 |
| Hierarchical test generation for digital systems M Brik, G Jervan, A Markus, J Raik, R Ubar Mixed Design of Integrated Circuits and Systems, 131-136, 1998 | 3 | 1998 |
| Hierarchical test generation for finite state machines M Brik, R Ubar Proc. of the 4th Baltic Electronics Conference, 319-324, 1994 | 3 | 1994 |
| Hardware close programming for freshmen H Kruus, M Brik, M Kruus, P Ruberg, V Viies, P Ellervee 10th European Workshop on Microelectronics Education (EWME), 93-96, 2014 | 2 | 2014 |
| Teaching research in the laboratory using diagnosis environment for digital systems S Kostin, R Ubar, J Raik, M Aarna, M Brik, HD Wuttke 2009 EAEEIE Annual Conference, 1-4, 2009 | 2 | 2009 |
| MIXED-LEVEL TEST GENERATOR FOR DIGITAL SYSTEMS1 M BRIK, G JERVAN, A MARKUS, P PAOMETS, J RAIK, R UBAR Proceedings of the Estonian Academy of Sciences, Engineering 3 (4), 271-282, 1997 | 2 | 1997 |
| A Hierarchical Automatic Test Pattern Generator Based on Using Alternative Graphs M Brik, G Jervan, A Markus, J Raik, R Ubar Proc. of the 4-th International Workshop on Computer Aided Design of Modern …, 0 | 2 | |
| On Using Genetic Algorithm for Test Generation M Brik, E Ivask, J Raik, R Ubar Proc. of the 9th Biennial Baltic Electronics Conference, 233-236, 2004 | 1 | 2004 |
| A Tool for Teaching Hierarchical Fault Diagnosis in Digital Circuits R Ubar, S Kostin, E Orasson, T Evartson, M Brik 9th, 109, 2012 | | 2012 |
| Hierarchical physical defect reasoning in digital circuits. S Kostin, R Ubar, J Raik, M Brik Estonian Journal of Engineering 17 (3), 2011 | | 2011 |
| Diagnostic modeling of microprocessors with high-level decision diagrams R Ubar, J Raik, A Jutman, M Jenihhin, M Brik, M Instenberg, HD Wuttke 2008 11th International Biennial Baltic Electronics Conference, 147-150, 2008 | | 2008 |
| Functional Test Generation for Finite State Machines R Ubar, M Brik, A Jutman, J Raik, T Bengtsson, S Kumar 2006 International Biennial Baltic Electronics Conference, 1-4, 2006 | | 2006 |
| Mixed-level defect simulation in data-paths of digital systems R Ubar, J Raik, E Ivask, M Brik 2002 23rd International Conference on Microelectronics. Proceedings (Cat. No …, 2002 | | 2002 |
| Defect-oriented mixed-level fault simulation in digital systems R Ubar, J Raik, E Ivask, M Brik Facta universitatis-series: Electronics and Energetics 15 (1), 123-136, 2002 | | 2002 |
| Defect-Oriented Mixed-Level Fault Ëimulation in Digital Ëystems R Ubar, J Raik, E Ivask, M Brik | | |
| ISSN 1736-7530 (electronic) ISSN 1736-6046 (print) Formerly: Proceedings of the Estonian Academy of Sciences, series Physics & Mathematics and Chemistry Published since 1952 AB Verbitsky, Y Vertsimakha, S Studzinski, S Bereznev, I Golovtsov, ... | | |
