| Parallel triangle counting and k-truss identification using graph-centric methods C Voegele, YS Lu, S Pai, K Pingali 2017 IEEE High Performance Extreme Computing Conference (HPEC), 1-7, 2017 | 46 | 2017 |
| An open-source eda flow for asynchronous logic S Ataei, W Hua, Y Yang, R Manohar, YS Lu, J He, S Maleki, K Pingali IEEE Design & Test 38 (2), 27-37, 2021 | 15 | 2021 |
| Cyclone: A static timing and power engine for asynchronous circuits W Hua, YS Lu, K Pingali, R Manohar 2020 26th IEEE International Symposium on Asynchronous Circuits and Systems …, 2020 | 15 | 2020 |
| Unlocking fine-grain parallelism for AIG rewriting V Possani, YS Lu, A Mishchenko, K Pingali, R Ribas, A Reis 2018 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 1-8, 2018 | 12 | 2018 |
| Can parallel programming revolutionize EDA tools? YS Lu, K Pingali Advanced Logic Synthesis, 21-41, 2018 | 9 | 2018 |
| Automatic generation of high-speed accurate tlm models for out-of-order pipelined bus CK Lo, ML Li, LC Chen, YS Lu, RS Tsay, HY Huang, JC Yeh ACM Transactions on Embedded Computing Systems (TECS) 13 (1s), 1-25, 2013 | 3 | 2013 |
| Deadlock free synchronization synthesizer for must-happen-before relations in parallel programs and method thereof YS Lu, HL Pai, MH Wu, RS Tsay US Patent App. 13/455,659, 2013 | 1 | 2013 |
| A non-intrusive timing synchronization interface for hardware-assisted HW/SW co-simulation YH Huang, YS Lu, HI Wu, RS Tsay Proceedings of the 49th Annual Design Automation Conference, 127-132, 2012 | 1 | 2012 |
| Toward a digital flow for asynchronous VLSI systems S Ataei, J He, W Hua, YS Lu, S Maleki, Y Yang, K Pingali, R Manohar 2nd Workshop on Open-Source EDA Technology (WOSET), 0 | 1 | |
| Effectively parallelizing electronic design automation algorithms using the operator formulation YS Lu | | 2022 |
| interact: An Interactive Design Environment for Asynchronous Logic J He, W Hua, YS Lu, S Maleki, Y Yang, K Pingali, R Manohar | | |
| A Digital Flow for Asynchronous VLSI Systems: Status Update U Agarwal, S Ataei, J He, W Hua, YS Lu, S Maleki, Y Yang, K Pingali, ... | | |
| ParallelClosure: A Parallel Design Optimizer for Timing Closure YS Lu, W Hua, R Manohar, K Pingali | | |
| Parallel Tools for Asynchronous VLSI Systems YS Lu, S Ataei, J He, W Hua, S Maleki, Y Yang, M Burtscher, K Pingali, ... | | |
| Automatic Generation for Efficient Software TLM at Multiple Abstraction Layers MH Wu, YS Lu, WC Lee, CY Chuang, RS Tsay | | |
