| Evidence for the utility of quantum computing before fault tolerance Y Kim, A Eddins, S Anand, KX Wei, E Van Den Berg, S Rosenblatt, ... Nature 618 (7965), 500-505, 2023 | 431 | 2023 |
| Demonstration of quantum volume 64 on a superconducting quantum computing system P Jurcevic, A Javadi-Abhari, LS Bishop, I Lauer, DF Bogorin, M Brink, ... Quantum Science and Technology 6 (2), 025020, 2021 | 404 | 2021 |
| Strained silicon MOSFET technology JL Hoyt, HM Nayfeh, S Eguchi, I Aberg, G Xia, T Drake, EA Fitzgerald, ... Digest. International Electron Devices Meeting,, 23-26, 2002 | 380 | 2002 |
| High performance 14nm SOI FinFET CMOS technology with 0.0174µm2 embedded DRAM and 15 levels of Cu metallization CH Lin, B Greene, S Narasimha, J Cai, A Bryant, C Radens, V Narayanan, ... 2014 IEEE International Electron Devices Meeting, 3.8. 1-3.8. 3, 2014 | 180 | 2014 |
| High performance 45-nm SOI technology with enhanced strain, porous low-k BEOL, and immersion lithography P Agnello, T Ivers, C Warm, R Wise, R Wachnik, D Schepis, S Sankaran, ... 2006 International Electron Devices Meeting, 1-4, 2006 | 133 | 2006 |
| A physically based analytical model for the threshold voltage of strained-Si n-MOSFETs HM Nayfeh, JL Hoyt, DA Antoniadis IEEE Transactions on electron Devices 51 (12), 2069-2072, 2004 | 107 | 2004 |
| Influence of high channel doping on the inversion layer electron mobility in strained silicon n-MOSFETs HM Nayfeh, CW Leitz, AJ Pitera, EA Fitzgerald, JL Hoyt, DA Antoniadis IEEE Electron Device Letters 24 (4), 248-250, 2003 | 76 | 2003 |
| High performance 65 nm SOI technology with enhanced transistor strain and advanced-low-K BEOL WH Lee, A Waite, H Nii, HM Nayfeh, V McGahay, H Nakayama, D Fried, ... IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest., 4 …, 2005 | 69 | 2005 |
| A 7nm CMOS technology platform for mobile and high performance compute application S Narasimha, B Jagannathan, A Ogino, D Jaeger, B Greene, C Sheraw, ... 2017 IEEE International Electron Devices Meeting (IEDM), 29.5. 1-29.5. 4, 2017 | 64 | 2017 |
| Metal gate MOSFET by full semiconductor metal alloy conversion HM Nayfeh, M Kumar, S Fang, JT Kedzierski, C Cabral Jr US Patent 7,151,023, 2006 | 57 | 2006 |
| Electron inversion layer mobility in strained-Si n-MOSFETs with high channel doping concentration achieved by ion implantation HM Nayfeh, JL Hoyt, CW Leitz, AJ Pitera, EA Fitzgerald, DA Antoniadis 60th DRC. Conference Digest Device Research Conference, 43-44, 2002 | 49 | 2002 |
| Advanced gate stacks with fully silicided (FUSI) gates and high-/spl kappa/dielectrics: Enhanced performance at reduced gate leakage EP Gusev, C Cabral, BP Under, YH Kim, K Maitra, E Carrier, H Nayfeh, ... IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004., 79-82, 2004 | 43 | 2004 |
| Infrared spectroscopy and secondary ion mass spectrometry of luminescent, nonluminescent, and metal quenched porous silicon J Hilliard, D Andsager, L Abu Hassan, HM Nayfeh, MH Nayfeh Journal of applied physics 76 (4), 2423-2428, 1994 | 37 | 1994 |
| Re‐establishment of photoluminescence in Cu quenched porous silicon by acid treatment JE Hilliard, HM Nayfeh, MH Nayfeh Journal of applied physics 77 (8), 4130-4132, 1995 | 34 | 1995 |
| Impact of ion implantation damage and thermal budget on mobility enhancement in strained-Si n-channel MOSFETs G Xia, HM Nayfeh, ML Lee, EA Fitzgerald, DA Antoniadis, DH Anjum, J Li, ... IEEE transactions on electron devices 51 (12), 2136-2144, 2004 | 29 | 2004 |
| Evaluating the influence of various body-contacting schemes on single event transients in 45-nm SOI CMOS KA Moen, SD Phillips, EP Wilcox, JD Cressler, H Nayfeh, AK Sutton, ... IEEE Transactions on Nuclear Science 57 (6), 3366-3372, 2010 | 26 | 2010 |
| Butted SOI junction isolation structures and devices and method of fabrication JB Johnson, S Narasimha, HM Nayfeh, V Ontalus, RR Robison US Patent 8,741,725, 2014 | 25 | 2014 |
| IEDM Tech. Dig. JL Hoyt, HM Nayfeh, SA Eguchi IEDM Tech. Dig 23, 2002 | 25 | 2002 |
| Trade-offs between RF performance and total-dose tolerance in 45-nm RF-CMOS R Arora, EX Zhang, S Seth, JD Cressler, DM Fleetwood, RD Schrimpf, ... IEEE Transactions on Nuclear Science 58 (6), 2830-2837, 2011 | 24 | 2011 |
| Stress liner surrounded facetless embedded stressor mosfet BY Kim, SA Butt, X Chen, SJJ Jeng, HM Nayfeh, D Wehella-Gamage US Patent App. 11/616,730, 2008 | 24 | 2008 |
