| Stacked nanosheet gate-all-around transistor to enable scaling beyond FinFET N Loubet, T Hook, P Montanini, CW Yeung, S Kanakasabapathy, ... 2017 symposium on VLSI technology, T230-T231, 2017 | 770 | 2017 |
| High acceptor level doping in silicon germanium MA Ebrish, O Gluschenkov, S Mochizuki, A Reznicek US Patent 9,799,736, 2017 | 307 | 2017 |
| A 7nm FinFET technology featuring EUV patterning and dual strained high mobility channels R Xie, P Montanini, K Akarvardar, N Tripathi, B Haran, S Johnson, T Hook, ... 2016 IEEE international electron devices meeting (IEDM), 2.7. 1-2.7. 4, 2016 | 175 | 2016 |
| Defect-free strain relaxed buffer layer P Morin, K Cheng, J Fronheiser, X Cai, J Li, S Mochizuki, R Xie, H He, ... US Patent App. 14/588,221, 2016 | 79 | 2016 |
| FINFET technology featuring high mobility SiGe channel for 10nm and beyond D Guo, G Karve, G Tsutsui, KY Lim, R Robison, T Hook, R Vega, D Liu, ... 2016 IEEE Symposium on VLSI Technology, 1-2, 2016 | 65 | 2016 |
| Sub- -cm2 n-Type Contact Resistivity for FinFET Technology H Niimi, Z Liu, O Gluschenkov, S Mochizuki, J Fronheiser, J Li, ... IEEE Electron Device Letters 37 (11), 1371-1374, 2016 | 56 | 2016 |
| Forming wrap-around silicide contact on finFET D Guo, H Jagannathan, Z Liu, S Mochizuki US Patent 9,318,581, 2016 | 55 | 2016 |
| Strain engineering in functional materials G Tsutsui, S Mochizuki, N Loubet, SW Bedell, DK Sadana AIP Advances 9 (3), 2019 | 42 | 2019 |
| Parasitic resistance reduction strategies for advanced CMOS FinFETs beyond 7nm H Wu, O Gluschenkov, G Tsutsui, C Niu, K Brew, C Durfee, C Prindle, ... 2018 IEEE International Electron Devices Meeting (IEDM), 35.4. 1-35.4. 4, 2018 | 40 | 2018 |
| Semiconductor device and method of manufacturing the semiconductor device S Mochizuki, G Tsutsui, R Sreenivasan, P Kerber, QC Ouyang, ... US Patent 9,812,556, 2017 | 39 | 2017 |
| FinFET performance with Si: P and Ge: Group-III-Metal metastable contact trench alloys O Gluschenkov, Z Liu, H Niimi, S Mochizuki, J Fronheiser, X Miao, J Li, ... 2016 IEEE International Electron Devices Meeting (IEDM), 17.2. 1-17.2. 4, 2016 | 39 | 2016 |
| Low resistance source drain contact formation O Gluschenkov, Z Liu, S Mochizuki, H Niimi, CC Yeh US Patent 9,972,682, 2018 | 36 | 2018 |
| Stacked Gate-All-Around Nanosheet pFET with Highly Compressive Strained Si1-xGex Channel S Mochizuki, M Bhuiyan, H Zhou, J Zhang, E Stuckert, J Li, K Zhao, ... 2020 IEEE International Electron Devices Meeting (IEDM), 2.3. 1-2.3. 4, 2020 | 34 | 2020 |
| Self-aligned air gap spacer for nanosheet CMOS devices S Mochizuki, A Reznicek, JM Rubin, J Wang US Patent 9,954,058, 2018 | 32 | 2018 |
| Selective GeOx-scavenging from interfacial layer on Si1−xGex channel for high mobility Si/Si1−xGex CMOS application CH Lee, H Kim, P Jamison, RG Southwick, S Mochizuki, K Watanabe, ... 2016 IEEE Symposium on VLSI Technology, 1-2, 2016 | 32 | 2016 |
| Local strain in SiGe/Si heterostructures analyzed by X-ray microdiffraction S Mochizuki, A Sakai, N Taoka, O Nakatsuka, S Takeda, S Kimura, ... Thin Solid Films 508 (1-2), 128-131, 2006 | 32 | 2006 |
| Self-aligned air gap spacer for nanosheet CMOS devices S Mochizuki, A Reznicek, JM Rubin, J Wang US Patent 10,243,043, 2019 | 31 | 2019 |
| Vertical-transport nanosheet technology for CMOS scaling beyond lateral-transport devices H Jagannathan, B Anderson, CW Sohn, G Tsutsui, J Strane, R Xie, S Fan, ... 2021 IEEE International Electron Devices Meeting (IEDM), 26.1. 1-26.1. 4, 2021 | 30 | 2021 |
| Ti and NiPt/Ti liner silicide contacts for advanced technologies P Adusumilli, E Alptekin, M Raymond, N Breil, F Chafik, C Lavoie, ... 2016 IEEE Symposium on VLSI Technology, 1-2, 2016 | 30 | 2016 |
| Nanosheet device with close source drain proximity VS Basker, S Mochizuki, A Reznicek US Patent 10,439,049, 2019 | 27 | 2019 |
