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Citations per year
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Cited by
All
Since 2019
Citations
21
21
h-index
1
1
i10-index
1
1
0
10
5
2020
2021
2022
2023
1
4
10
6
Follow
Víctor Jiménez Arador
Research Engineer,
Barcelona Supercomputing Center
Verified email at bsc.es
computer architecture
computer engineering
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Year
An academic risc-v silicon implementation based on open-source components
J Abella, C Bulla, G Cabo, FJ Cazorla, A Cristal, M Doblas, R Figueras, ...
2020 XXXV conference on design of circuits and integrated systems (DCIS), 1-6
, 2020
21
2020
DVINO: A RISC-V vector processor implemented in 65nm technology
G Cabo Pitarch, G Candon, X Carril, M Doblas Font, ...
DCIS 2022: proceedings of the 37th Conference on Design of Circuits and …
, 2022
2022
Design under test interface implementation and stimulus in the verification of a RISC-V vector accelerator
V Jiménez Arador
Universitat Politčcnica de Catalunya
, 2021
2021
Verification Strategy for a RISC-V Core Design
V Jiménez Arador
Universitat Politčcnica de Catalunya
, 2019
2019
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