| Background Digital Calibration of Comparator Offsets in Pipeline ADCs AJ Ginés, E Peralías, A Rueda IEEE Transactions on Very Large Scale Integration (VLSI) Systems 23 (7 …, 2015 | 26 | 2015 |
| A mixed-signal design reuse methodology based on parametric behavioural models with non-ideal effects AJ Ginés, E Peralías, A Rueda, NM Madrid, R Seepold Design, Automation and Test in Europe Conference and Exhibition, 2002 …, 2002 | 26 | 2002 |
| Blind adaptive estimation of integral nonlinear errors in ADCs using arbitrary input stimulus AJ Gines Arteaga, EJ Peralías, A Rueda Instrumentation and Measurement, IEEE Transactions on 60 (2), 452-461, 2011 | 23 | 2011 |
| Black-Box Calibration for ADCs With Hard Nonlinear Errors Using a Novel INL-Based Additive Code: A Pipeline ADC Case Study AJ Ginés, EJ Peralías, A Rueda IEEE Transactions on Circuits and Systems I: Regular Papers, 2017 | 21 | 2017 |
| Design trade-offs for on-chip driving of high-speed high-performance ADCs in static BIST applications AJ Gines, E Peralias, G Leger, A Rueda, G Renaud, MJ Barragan, S Mir 2016 IEEE 21st International Mixed-Signal Testing Workshop (IMSTW), 1-6, 2016 | 21 | 2016 |
| A compact R-2R DAC for BIST applications A Rabal, A Otin, I Urriza, AJ Gines, G Leger, A Rueda 2016 IEEE 21st International Mixed-Signal Testing Workshop (IMSTW), 1-6, 2016 | 21* | 2016 |
| On Chopper Effects in Discrete-Time< formula formulatype= G Léger, AJ Gines Arteaga, EJ Peralías Macías, A Rueda Circuits and Systems I: Regular Papers, IEEE Transactions on 57 (9), 2438-2449, 2010 | 20* | 2010 |
| Assessing AMS-RF test quality by defect simulation. V Gutierrez, A Gines, G Leger IEEE Transactions on Device and Materials Reliability, 2019 | 18 | 2019 |
| INL systematic reduced-test technique for Pipeline ADCs E Peralias, A Gines, A Rueda Test Symposium (ETS), 2014 19th IEEE European, 1-6, 2014 | 17 | 2014 |
| Linearity test of high-speed high-performance ADCs using a self-testable on-chip generator AJ Gines, E Peralias, G Leger, A Rueda, G Renaud, MJ Barragan, S Mir 2016 21th IEEE European Test Symposium (ETS), 1-6, 2016 | 13 | 2016 |
| A 1.2 V 5.14 mW quadrature frequency synthesizer in 90nm CMOS technology for 2.4 GHz ZigBee applications AJ Gines, R Doldán, A Villegas, AJ Acosta, MA Jalón, D Vázquez, ... Institute of Electrical and Electronics Engineers, 2008 | 13 | 2008 |
| Digital background calibration technique for pipeline ADCs with multi-bit stages AJ Ginés, EJ Peralías, A Rueda Integrated Circuits and Systems Design, 2003. SBCCI 2003. Proceedings. 16th …, 2003 | 13 | 2003 |
| Likelihood-sampling adaptive fault simulation G Leger, A Gines Mixed Signals Testing Workshop (IMSTW), 2017 International, 1-6, 2017 | 12 | 2017 |
| A survey on digital background calibration of ADCs AJ Ginés, EJ Peralías, A Rueda Circuit Theory and Design, 2009. ECCTD 2009. European Conference on, 101-104, 2009 | 12 | 2009 |
| A 76nW, 4kS/s 10-bit SAR ADC with offset cancellation for biomedical applications M Delgado-Restituto, M Carrasco-Robles, R Fiorelli, AJ Ginés-Arteaga, ... 2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), 421-424, 2016 | 11 | 2016 |
| Low-jitter differential clock driver circuits for high-performance high-resolution ADCs J Nunez, AJ Gines, EJ Peralias, A Rueda Design of Circuits and Integrated Systems (DCIS), 2015 Conference on, 1-4, 2015 | 11 | 2015 |
| Description of SAR ADCs with Digital Redundancy using a Unified Hardware-Based Approach A Gines, A Lopez-Angulo, E Peralias, A Rueda Circuits and Systems (ISCAS), 2018 IEEE International Symposium on, 1-5, 2018 | 8 | 2018 |
| On the limits of machine learning-based test: A calibrated mixed-signal system case study MJ Barragan, G Leger, A Gines, E Peralias, A Rueda 2017 Design, Automation & Test in Europe Conference & Exhibition (DATE), 79-84, 2017 | 7 | 2017 |
| Sigma-delta testability for pipeline A/D converters A Gines, G Leger Design, Automation and Test in Europe Conference and Exhibition (DATE), 2014 …, 2014 | 7 | 2014 |
| Improved background algorithms for Pipeline ADC full calibration AJ Ginés, EJ Peralias, A Rueda Circuits and Systems, 2007. ISCAS 2007. IEEE International Symposium on …, 2007 | 7 | 2007 |
Eduardo PeraliasInstituto de Microelectrónica de Sevilla (IMSE-CSIC), Universidad de SevillaVerified email at imse-cnm.csic.es
