| Performance and Energy Impact of Enhanced Cache Replacement Policy on STT-MRAM LLC PY Péneau, D Novo, F Bruguier, L Torres, G Sassatelli, A Gamatié | | 2021 |
| Towards a Flexible and Comprehensive Evaluation Approach for Adressing NVM Integration in Cache Hierarchy PY Péneau, F Bruguier, D Novo, G Sassatelli, A Gamatié | 2 | 2021 |
| TRAITOR: A Low-Cost Evaluation Platform for Multifault Injection L Claudepierre, PY Péneau, D Hardy, E Rohou ASIACCS 2021-16th ACM ASIA Conference on Computer and Communications …, 2021 | 15 | 2021 |
| NOP-Oriented Programming: Should we Care? PY Péneau, L Claudepierre, D Hardy, E Rohou 2020 IEEE European Symposium on Security and Privacy Workshops (EuroS&PW …, 2020 | 8 | 2020 |
| Intégration de technologies de mémoires non volatiles émergentes dans la hiérarchie de caches pour améliorer l'efficacité énergétique PY Péneau Université Montpellier, 2018 | 1 | 2018 |
| Improving the Performance of STT-MRAM LLC Through Enhanced Cache Replacement Policy PY Péneau, D Novo, F Bruguier, L Torres, G Sassatelli, A Gamatié International Conference on Architecture of Computing Systems, 168-180, 2018 | 10 | 2018 |
| Performance and energy assessment of last-level cache replacement policies PY Péneau, D Novo, F Bruguier, G Sassatelli, A Gamatié 2017 First International Conference on Embedded & Distributed Systems (EDiS …, 2017 | 7 | 2017 |
| MAGPIE: System-level Evaluation of Manycore Systems with Emerging Memory Technologies T Delobelle, PY Péneau, A Gamatié, F Bruguier, S Senni, G Sassatelli, ... 2nd International Workshop on Emerging Memory Solutions (EMS), 2017 | 14 | 2017 |
| Embedded systems to high performance computing using STT-MRAM S Senni, T Delobelle, O Coi, PY Peneau, L Torres, A Gamatie, P Benoit, ... Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017 …, 2017 | 10 | 2017 |
| Exploiting Large Memory using 32-bit Energy-Efficient Manycore Architectures ML Karaoui, PY Péneau, QL Meunier, F Wajsbürt, A Greiner IEEE 10th International Symposium on Embedded Multicore/Many-core Systems-on …, 2016 | | 2016 |
| Loop Optimization in Presence of STT-MRAM Caches: a Study of Performance-Energy Tradeoffs PY Péneau, R Bouziane, A Gamatié, E Rohou, F Bruguier, G Sassatelli, ... 26th International Workshop on Power and Timing Modeling, Optimization and …, 2016 | 13 | 2016 |
| Migration de processus pour un multi-noyau large échelle PY Péneau, ML Karaoui, F Wajsbürt Compas: Conférence en Parallélisme, Architecture et Système, 8, 2016 | | 2016 |
| Flot automatique d’évaluation pour l’exploration d’architectures à base de mémoires non volatiles T Delobelle, PY Péneau, S Senni, F Bruguier, A Gamatié, G Sassatelli, ... Compas: Conférence en Parallélisme, Architecture et Système, 2016 | 4 | 2016 |
| Migration de processus pour un multi-noyau large échelle PY Péneau Université Pierre and Marie Curie, 2015 | | 2015 |
Gilles SassatelliLIRMM CNRS / University of MontpellierVerified email at lirmm.fr
