| Design and analysis of electrostatic doped Schottky barrier CNTFET based low power SRAM A Singh, M Khosla, B Raj AEU-International Journal of Electronics and Communications 80, 67-72, 2017 | 57 | 2017 |
| Design and analysis of a gate-all-around CNTFET-based SRAM cell G Saiphani Kumar, A Singh, B Raj Journal of Computational Electronics 17, 138-145, 2018 | 48 | 2018 |
| Design and analysis of dynamically configurable electrostatic doped carbon nanotube tunnel FET A Singh, M Khosla, B Raj Microelectronics Journal 85, 17-24, 2019 | 45 | 2019 |
| Comparative analysis of carbon nanotube field effect transistor and nanowire transistor for low power circuit design A Singh, M Khosla, B Raj Journal of Nanoelectronics and Optoelectronics 11 (3), 388-393, 2016 | 39 | 2016 |
| Impact of double gate geometry on the performance of carbon nanotube field effect transistor structures for low power digital design AK Bhardwaj, S Gupta, B Raj, A Singh Journal of Computational and Theoretical Nanoscience 16 (5-6), 1813-1820, 2019 | 36 | 2019 |
| Analysis of electrostatic doped Schottky barrier carbon nanotube FET for low power applications A Singh, M Khosla, B Raj Journal of Materials Science: Materials in Electronics 28, 1762-1768, 2017 | 30 | 2017 |
| Circuit compatible model for electrostatic doped Schottky barrier CNTFET A Singh, M Khosla, B Raj Journal of Electronic Materials 45, 5381-5390, 2016 | 27 | 2016 |
| Modeling and simulation of carbon nanotube field effect transistor and its circuit application A Singh, DK Saini, D Agarwal, S Aggarwal, M Khosla, B Raj Journal of Semiconductors 37 (7), 074001, 2016 | 27 | 2016 |
| Compact model for ballistic single wall CNTFET under quantum capacitance limit A Singh, M Khosla, B Raj Journal of Semiconductors 37 (10), 104001, 2016 | 24 | 2016 |
| Comparative analysis of carbon nanotube field effect transistors A Singh, M Khosla, B Raj 2015 IEEE 4th Global Conference on Consumer Electronics (GCCE), 552-555, 2015 | 18 | 2015 |
| CNTFET modeling and low power SRAM cell design A Singh, M Khosla, B Raj 2016 IEEE 5th Global Conference on Consumer Electronics (GCCE), 1-4, 2016 | 11 | 2016 |
| Design and analysis of negative capacitance based dual material dopingless tunnel FET ASMSASNKSIAS Anand Superlattices and Microstructures, 2021 | 9 | 2021 |
| Implementation of gate-all-around gate-engineered charge plasma nanowire FET-based common source amplifier S Singh, LR Solay, S Anand, N Kumar, R Ranjan, A Singh Micromachines 14 (7), 1357, 2023 | 7 | 2023 |
| Doping-less TFET based common source amplifier implementation and behaviour analysis under symmetric and asymmetric conditions A Bhardwaj, LR Solay, N Kumar, SI Amin, A Singh, B Raj, P Kumar, ... Silicon 14 (18), 12251-12260, 2022 | 5 | 2022 |
| Various applications of nanowires Z Azam, A Singh Innovative Applications of Nanowires for Circuit Design, 17-53, 2021 | 3 | 2021 |
| Gate All around CNTFET based Ternary Content Addressable Memory SSGA Singh ECS Journal of Solid State Science and Technology 11 (6), 061006, 2022 | 2 | 2022 |
| Design and Implementation of Negative Capacitance Based Electrostatic Doped Double Gate Tunnel Field Effect Transistor MA Lone, LR Solay, A Singh, SI Amin, S Anand Silicon 14 (18), 12293-12301, 2022 | 1 | 2022 |
| Compact Model for a Negative Capacitance-Based Top-Gated Carbon-Nanotube Field-Effect Transistor S Mairaj, A Singh Journal of Electronic Materials, 1-15, 2024 | | 2024 |
| Low power Circuit Design Using Dynamic GDI Technique in CNTFET Technology AS Rehal Proceedings of the 18th ACM International Symposium on Nanoscale …, 2023 | | 2023 |
| Investigating the Impact of Intermediate Modulation Layer in RRAM on Multilevel Perceptron Performance IH Wani, A Singh 2023 IEEE Silchar Subsection Conference (SILCON), 1-6, 2023 | | 2023 |
Dr. Balwinder RajNational Institute of Technology JalandharVerified email at nitj.ac.in
