| Analysis and design of current starved ring VCO S Suman, KG Sharma, PK Ghosh Electrical, Electronics, and Optimization Techniques (ICEEOT), International …, 2016 | 73 | 2016 |
| High performance full adder cell: A comparative analysis T Sharma, KG Sharma, BP Singh Students' Technology Symposium (TechSym), 2010 IEEE, 156-160, 2010 | 46 | 2010 |
| Design of Improved Performance Voltage Controlled Ring Oscillator B Kinger, S Suman, KG Sharma, PK Ghosh Advanced Computing & Communication Technologies (ACCT), 2015 Fifth …, 2015 | 43 | 2015 |
| Design and analysis of low power 1-bit full adder cell D Sinha, T Sharma, KG Sharma, BP Singh Electronics Computer Technology (ICECT), 2011 3rd International Conference …, 2011 | 39 | 2011 |
| 2-Bit magnitude comparator using GDI technique V Shekhawat, T Sharma, KG Sharma Recent Advances and Innovations in Engineering (ICRAIE), 2014, 1-5, 2014 | 31 | 2014 |
| Modified SET D-flip flop design for low-power VLSI applications KG Sharma, T Sharma, BP Singh, M Sharma Devices and Communications (ICDeCom), 2011 International Conference on, 1-5, 2011 | 30 | 2011 |
| Wallace Tree Multiplier Designs: A Performance Comparison Review H Bansal, KG Sharma, T Sharma Innovative Systems Design and Engineering 5 (5), 60-67, 2014 | 24* | 2014 |
| High speed, low power 8t full adder cell with 45% improvement in threshold loss problem T Sharma, KG Sharma, BP Singh, N Arora Proceedings of the 12th international conference on Networking, VLSI and …, 2010 | 19 | 2010 |
| Design of PLL using improved performance ring VCO S Suman, KG Sharma, PK Ghosh Electrical, Electronics, and Optimization Techniques (ICEEOT), International …, 2016 | 18 | 2016 |
| Performance Analysis of Voltage Controlled Ring Oscillators S Suman, KG Sharma, PK Ghosh Proceedings of the International Congress on Information and Communication …, 2016 | 14 | 2016 |
| Double Gate MOSFET circuit design Ruchika, T Sharma, KG Sharma Recent Advances and Innovations in Engineering (ICRAIE), 2014, 1-4, 2014 | 14* | 2014 |
| Design of Ring Oscillator based VCO with Improved Performance SS Vaishali, KG Sharma, PK Ghosh, S Lakshmangarh Innovative Systems Design and Engineering-IISTE 5 (2), 31-41, 2014 | 14 | 2014 |
| Efficient interconnect design with novel repeater insertion for low power applications T Sharma, KG Sharma, BP Singh, N Arora WSEAS Transactions on Circuits and Systems 9 (3), 153-162, 2010 | 13 | 2010 |
| 250 MHz Multiphase Delay Locked Loop for Low Power Applications S Suman, KG Sharma, PK Ghosh International Journal of Electrical and Computer Engineering (IJECE) 7 (6), 2017 | 11 | 2017 |
| Ultra low power 1-bit full adder D Sinha, T Sharma, KG Sharma, BP Singh International Journal of Computer Applications 1, 2011 | 10 | 2011 |
| A novel CMOS 1-bit 8T full adder cell T Sharma, KG Sharma, BP Singh, N Arora WSEAS Transactions on Systems 9 (3), 317-326, 2010 | 9 | 2010 |
| Low Power Magnitude Comparator Circuit Design V Shekhawat, T Sharma, K G Sharma International Journal of Computer Applications 94 (1), 22-24, 2014 | 8 | 2014 |
| Design and Analysis of 8T Full Adder Cell Using Double Gate MOSFET TS Ruchika, KG Sharma International Journal of Advances in Electronics Engineering–IJAEE, 2013 | 8 | 2013 |
| SET D-flip flop design for portable applications M Sharma, KG Sharma, T Sharma, BP Singh, N Arora Power Electronics (IICPE), 2010 India International Conference on, 1-5, 2011 | 8 | 2011 |
| High speed array multipliers based on 1-bit full adders T Sharma, BP Singh, KG Sharma, N Arora Int. J. of Recent Trends in Engineering and Technology 4 (4), 26-28, 2010 | 8 | 2010 |
