| Self-heating on bulk FinFET from 14nm down to 7nm node D Jang, E Bury, R Ritzenthaler, MG Bardon, T Chiarella, K Miyaguchi, ... 2015 IEEE International Electron Devices Meeting (IEDM), 11.6. 1-11.6. 4, 2015 | 95 | 2015 |
| A physically unclonable function using soft oxide breakdown featuring 0% native BER and 51.8 fJ/bit in 40-nm CMOS KH Chuang, E Bury, R Degraeve, B Kaczer, D Linten, I Verbauwhede IEEE Journal of Solid-State Circuits 54 (10), 2765-2776, 2019 | 64 | 2019 |
| A brief overview of gate oxide defect properties and their relation to MOSFET instabilities and device and circuit time-dependent variability B Kaczer, J Franco, P Weckx, PJ Roussel, V Putcha, E Bury, M Simicic, ... Microelectronics Reliability 81, 186-194, 2018 | 61 | 2018 |
| Experimental validation of self-heating simulations and projections for transistors in deeply scaled nodes E Bury, B Kaczer, P Roussel, R Ritzenthaler, K Raleva, D Vasileska, ... 2014 IEEE International Reliability Physics Symposium, XT. 8.1-XT. 8.6, 2014 | 52 | 2014 |
| Self-heating in FinFET and GAA-NW using Si, Ge and III/V channels E Bury, B Kaczer, D Linten, L Witters, H Mertens, N Waldron, X Zhou, ... 2016 IEEE International Electron Devices Meeting (IEDM), 15.6. 1-15.6. 4, 2016 | 49 | 2016 |
| Characterization of time-dependent variability using 32k transistor arrays in an advanced HK/MG technology P Weckx, B Kaczer, C Chen, J Franco, E Bury, K Chanda, J Watt, ... 2015 IEEE International Reliability Physics Symposium, 3B. 1.1-3B. 1.6, 2015 | 49 | 2015 |
| Reliability and variability of advanced CMOS devices at cryogenic temperatures A Grill, E Bury, J Michl, S Tyaginov, D Linten, T Grasser, B Parvais, ... 2020 IEEE International Reliability Physics Symposium (IRPS), 1-6, 2020 | 40 | 2020 |
| Origins and implications of increased channel hot carrier variability in nFinFETs B Kaczer, J Franco, M Cho, T Grasser, PJ Roussel, S Tyaginov, M Bina, ... 2015 IEEE International Reliability Physics Symposium, 3B. 5.1-3B. 5.6, 2015 | 38 | 2015 |
| Beyond interface: The impact of oxide border traps on InGaAs and Ge n-MOSFETs D Lin, A Alian, S Gupta, B Yang, E Bury, S Sioncke, R Degraeve, ... 2012 International Electron Devices Meeting, 28.3. 1-28.3. 4, 2012 | 34 | 2012 |
| Characterization of self-heating in high-mobility Ge FinFET pMOS devices E Bury, B Kaczer, J Mitard, N Collaert, NS Khatami, Z Aksamija, ... 2015 Symposium on VLSI Technology (VLSI Technology), T60-T61, 2015 | 33 | 2015 |
| Statistical assessment of the full VG/VDdegradation space using dedicated device arrays E Bury, B Kaczer, K Chuang, J Franco, P Weckx, A Chasin, M Simicic, ... 2017 IEEE International Reliability Physics Symposium (IRPS), 2D-5.1-2D-5.6, 2017 | 26 | 2017 |
| Physically unclonable function using CMOS breakdown position KH Chuang, E Bury, R Degraeve, B Kaczer, G Groeseneken, ... 2017 IEEE International Reliability Physics Symposium (IRPS), 4C-1.1-4C-1.7, 2017 | 26 | 2017 |
| The defect-centric perspective of device and circuit reliability—From gate oxide defects to circuits B Kaczer, J Franco, P Weckx, PJ Roussel, M Simicic, V Putcha, E Bury, ... Solid-State Electronics 125, 52-62, 2016 | 24 | 2016 |
| Array-Based Statistical Characterization of CMOS Degradation Modes and Modeling of the Time-Dependent Variability Induced by Different Stress Patterns in the $\{\boldsymbol {V … E Bury, A Chasin, M Vandemaele, S Van Beek, J Franco, B Kaczer, ... 2019 IEEE International Reliability Physics Symposium (IRPS), 1-6, 2019 | 23 | 2019 |
| Complete degradation mapping of stacked gate-all-around Si nanowire transistors considering both intrinsic and extrinsic effects A Chasin, E Bury, B Kaczer, J Franco, P Roussel, R Ritzenthaler, ... 2017 IEEE International Electron Devices Meeting (IEDM), 7.1. 1-7.1. 4, 2017 | 23 | 2017 |
| The defect-centric perspective of device and circuit reliability—From individual defects to circuits B Kaczer, J Franco, P Weckx, PJ Roussel, E Bury, M Cho, R Degraeve, ... 2015 45th European Solid State Device Research Conference (ESSDERC), 218-225, 2015 | 22 | 2015 |
| Self-heating-aware CMOS reliability characterization using degradation maps E Bury, A Chasin, B Kaczer, KH Chuang, J Franco, M Simicic, P Weckx, ... 2018 IEEE International Reliability Physics Symposium (IRPS), 2A. 3-1-2A. 3-6, 2018 | 20 | 2018 |
| Low-power DRAM-compatible replacement gate high-k/metal gate stacks R Ritzenthaler, T Schram, E Bury, A Spessot, C Caillat, V Srividya, ... Solid-state electronics 84, 22-27, 2013 | 20 | 2013 |
| NBTI in replacement metal gate SiGe core FinFETs: Impact of Ge concentration, fin width, fin rotation and interface passivation by high pressure anneals J Franco, B Kaczer, A Chasin, H Mertens, LÅ Ragnarsson, R Ritzenthaler, ... 2016 IEEE International Reliability Physics Symposium (IRPS), 4B-2-1-4B-2-7, 2016 | 19 | 2016 |
| Comparison of electrical performance of co-integrated forksheets and nanosheets transistors for the 2nm technological node and beyond R Ritzenthaler, H Mertens, G Eneman, E Simoen, E Bury, P Eyben, ... 2021 IEEE International Electron Devices Meeting (IEDM), 26.2. 1-26.2. 4, 2021 | 18 | 2021 |
