The gem5 simulator: Version 20.0+ J Lowe-Power, AM Ahmad, A Akram, M Alian, R Amslinger, M Andreozzi, ... arXiv preprint arXiv:2007.03152, 2020 | 257 | 2020 |
Compression-aware and performance-efficient insertion policies for long-lasting hybrid llcs C Escuin, AA Khan, P Ibánez, T Monreal, J Castrillon, V Viñals 2023 IEEE International Symposium on High-Performance Computer Architecture …, 2023 | 2 | 2023 |
L2C2: Last-level compressed-contents non-volatile cache and a procedure to forecast performance and lifetime C Escuin, P Ibáñez, D Navarro, T Monreal, JM Llabería, V Viñals Plos one 18 (2), 2023 | 2 | 2023 |
Hycsim: A rapid design space exploration tool for emerging hybrid last-level caches C Escuin, AA Khan, P Ibañez, T Monreal, V Viñals, J Castrillon System Engineering for constrained embedded systems, 53-58, 2022 | 2 | 2022 |
STT-RAM memory hierarchy designs aimed to performance, reliability and energy consumption C Escuín Blasco, T Monreal Arnal, JM Llaberia Griñó, V Viñals Yúfera, ... ACACES 2019: July 17, 2019, Fiuggi, Italy: poster abstracts, 231-234, 2019 | 2 | 2019 |
Leveraging Data Compression for Performance-Efficient and Long-Lasting NVM-based Last-Level Caches C Escuin, AA Khan, P Ibánez, T Monreal, D Navarro, JM Llaberıa, ... 14th Annual Non-Volatile Memory Workshop, 2023 | 1* | 2023 |
MNEMOSENE++: Scalable Multi-Tile Design with Enhanced Buffering and VGSOT-MRAM based Compute-in-Memory Crossbar Array C Escuin, F García-Redondo, M Zahedi, P Ibáñez, T Monreal, V Viñals, ... 2023 30th IEEE International Conference on Electronics, Circuits and Systems …, 2023 | | 2023 |
Pronóstico de capacidad efectiva y prestaciones en una cache no volátil de último nivel C Escuín Blasco, T Monreal Arnal, JM Llaberia Griñó, PE Ibáñez Marín, ... Avances en arquitectura y tecnología de computadore: Actas de las Jornadas …, 2021 | | 2021 |
Analysis and simulation of data prefetching algorithms for last-level cache memory C Escuín Blasco Universitat Politècnica de Catalunya, 2018 | | 2018 |
Three is not a crowd: ACPU-GPU-FPGA K-means implementation M Canales, DA Constantinescu, C Escuin, B Perez | | 2017 |