| Performance benefits of monolithically stacked 3-D FPGA M Lin, A El Gamal, YC Lu, S Wong Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions …, 2007 | 503 | 2007 |
| Thermal modeling for 3D-ICs with integrated microchannel cooling H Mizunuma, CL Yang, YC Lu Proceedings of the 2009 International Conference on Computer-Aided Design …, 2009 | 67 | 2009 |
| Thermal modeling and analysis for 3-D ICs with integrated microchannel cooling H Mizunuma, YC Lu, CL Yang IEEE Transactions on computer-aided design of integrated circuits and …, 2011 | 66 | 2011 |
| Deep co-occurrence feature learning for visual object recognition YF Shih, YM Yeh, YY Lin, MF Weng, YC Lu, YY Chuang Proceedings of the IEEE Conference on Computer Vision and Pattern …, 2017 | 45 | 2017 |
| Min/max on-chip inductance models and delay metrics YC Lu, M Celik, T Young, LT Pileggi Proceedings of the 38th annual Design Automation Conference, 341-346, 2001 | 43 | 2001 |
| Light field based digital refocusing using a DSLR camera with a pinhole array mask CC Chen, YC Lu, MS Su 2010 IEEE International Conference on Acoustics, Speech and Signal …, 2010 | 42 | 2010 |
| Signal/power integrity modeling of high-speed memory modules using chip-package-board coanalysis HH Chuang, WD Guo, YH Lin, HS Chen, YC Lu, YS Cheng, MZ Hong, ... IEEE transactions on electromagnetic compatibility 52 (2), 381-391, 2010 | 39 | 2010 |
| Adaptively banded smith-waterman algorithm for long reads and its hardware accelerator YL Liao, YC Li, NC Chen, YC Lu 2018 IEEE 29th International Conference on Application-specific Systems …, 2018 | 27 | 2018 |
| ABF-based TSV arrays with improved signal integrity on 3-D IC/interposers: Equivalent models and experiments CD Wang, YJ Chang, YC Lu, PS Chen, WC Lo, YP Chiou, TL Wu IEEE Transactions on Components, Packaging and Manufacturing Technology 3 …, 2013 | 27 | 2013 |
| BLASTP-ACC: Parallel architecture and hardware accelerator design for BLAST-based protein sequence alignment YC Li, YC Lu IEEE Transactions on Biomedical Circuits and Systems 13 (6), 1771-1782, 2019 | 25 | 2019 |
| Testing of TSV-induced small delay faults for 3-D integrated circuits CY Kuo, CJ Shih, YC Lu, JCM Li, K Chakrabarty IEEE Transactions on Very Large Scale Integration (VLSI) Systems 22 (3), 667-674, 2013 | 25 | 2013 |
| A fast analytical technique for estimating the bounds of on-chip clock wire inductance YC Lu, K Banerjee, M Celik, RW Dutton Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No …, 2001 | 25 | 2001 |
| Novel crosstalk modeling for multiple throughsilicon-vias (TSV) on 3-D IC: Experimental validation and application to Faraday cage design YJ Chang, HH Chuang, YC Lu, YP Chiou, TL Wu, PS Chen, SH Wu, ... Electrical Performance of Electronic Packaging and Systems (EPEPS), 2012 …, 2012 | 24 | 2012 |
| Low-light enhancement using a plug-and-play Retinex model with shrinkage mapping for illumination estimation YH Lin, YC Lu IEEE Transactions on Image Processing 31, 4897-4908, 2022 | 21 | 2022 |
| A pixel-based depth estimation algorithm and its hardware implementation for 4-D light field data CW Chang, MR Chen, PH Hsu, YC Lu 2014 IEEE International Symposium on Circuits and Systems (ISCAS), 786-789, 2014 | 15 | 2014 |
| An equation-based circuit model and its generation tool for 3-D IC power delivery networks with an emphasis on coupling effect CH Cheng, TY Cheng, CH Du, YC Lu, YP Chiou, S Liu, TL Wu IEEE Transactions on Components, Packaging and Manufacturing Technology 4 (6 …, 2014 | 15 | 2014 |
| Architecture for next-generation massively parallel maskless lithography system (MPML2) MS Su, KY Tsai, YC Lu, YH Kuo, TH Pei, JY Yen Alternative Lithographic Technologies II 7637, 394-401, 2010 | 15 | 2010 |
| A new method to improve accuracy of leakage current estimation for transistors with non-rectangular gates due to sub-wavelength lithography effects KY Tsai, MF You, YC Lu, PCW Ng 2008 IEEE/ACM International Conference on Computer-Aided Design, 286-291, 2008 | 15 | 2008 |
| A built-in technique for measuring substrate and power-supply digital switching noise using PMOS-based differential sensors and a waveform sampler in system-on-chip applications C Iorga, YC Lu, RW Dutton IEEE Transactions on Instrumentation and Measurement 56 (6), 2330-2337, 2007 | 14 | 2007 |
| Modeling of wave behavior of substrate noise coupling for mixed-signal IC design G Veronis, YC Lu, RW Dutton International Symposium on Signals, Circuits and Systems. Proceedings, SCS …, 2004 | 13 | 2004 |
Abbas El GamalElectrical Engineering, Stanford UniversityVerified email at ee.stanford.edu
