| An efficient hardware-based higher radix floating point MAC design MA Basiri M, NM Sk ACM Transactions on Design Automation of Electronic Systems (TODAES) 20 (1 …, 2014 | 23 | 2014 |
| Configurable folded IIR filter design NM Sk IEEE Transactions on Circuits and Systems II: Express Briefs 62 (12), 1144-1148, 2015 | 17 | 2015 |
| An efficient VLSI architecture for lifting based 1D/2D discrete wavelet transform NM Sk Microprocessors and Microsystems 47, 404-418, 2016 | 14 | 2016 |
| Flexible VLSI architectures for Galois field multipliers SK Shukla Integration 59, 109-124, 2017 | 13 | 2017 |
| Hardware optimizations for crypto implementations MMA Basiri, SK Shukla 2016 20th International Symposium on VLSI Design and Test (VDAT), 1-6, 2016 | 13 | 2016 |
| High speed multiplexer design using tree based decomposition algorithm NM Sk Microelectronics Journal 51, 99-111, 2016 | 13 | 2016 |
| Multiplication acceleration through quarter precision Wallace tree multiplier MMA Basiri, SC Nayak, NM Sk 2014 International Conference on Signal Processing and Integrated Networks …, 2014 | 12 | 2014 |
| High performance integer DCT architectures for HEVC NM Sk 2017 30th International Conference on VLSI Design and 2017 16th …, 2017 | 9 | 2017 |
| An efficient hardware based MAC design in digital filters with complex numbers MMA Basiri, NM Sk 2014 International Conference on Signal Processing and Integrated Networks …, 2014 | 9 | 2014 |
| An efficient vlsi architecture for convolution based dwt using mac NM Sk 2018 31st International Conference on VLSI Design and 2018 17th …, 2018 | 8 | 2018 |
| An efficient VLSI architecture for discrete Hadamard transform MMA Basiri, SKN Mahammad 2016 29th International Conference on VLSI Design and 2016 15th …, 2016 | 8 | 2016 |
| High precision and high speed handheld scientific calculator design using hardware based CORDIC algorithm S Kumar, NM Sk Procedia Engineering 64, 56-64, 2013 | 8* | 2013 |
| Versatile Architectures of Artificial Neural Network with Variable Capacity M Basiri Circuits, Systems, and Signal Processing 41 (11), 6333-6353, 2022 | 6 | 2022 |
| Multi-mode parallel and folded VLSI architectures for 1D-fast Fourier transform NM Sk Integration 55, 43-56, 2016 | 6 | 2016 |
| Memory Based Multiplier Design in Custom and FPGA Implementation MMA Basiri, SKN Mahammad Advances in Intelligent Informatics, 253-265, 2015 | 5 | 2015 |
| Reconfigurable Hardware Design for Polynomial Galois Field Arithmetic Operations H Inumarty 2020 24th International Symposium on VLSI Design and Test (VDAT), 1-5, 2020 | 4 | 2020 |
| Asynchronous hardware implementations for crypto primitives SK Shukla Microprocessors and Microsystems 64, 221-236, 2019 | 4 | 2019 |
| Efficient hardware-software codesigns of AES encryptor and RS-BCH encoder M Mohamed Asan Basiri, SK Shukla International Symposium on VLSI Design and Test, 3-15, 2018 | 4 | 2018 |
| Efficient VLSI architectures of lifting based 3D discrete wavelet transform MMA Basiri IET Computers & Digital Techniques 14 (6), 247-255, 2020 | 3 | 2020 |
| LFSR based versatile divider architectures for BCH and RS error correction encoders SK Shukla Microprocessors and Microsystems 71, 102902, 2019 | 3 | 2019 |
