| Hardware model checking competition 2014: an analysis and comparison of model checkers and benchmarks G Cabodi, C Loiacono, M Palena, P Pasini, D Patti, S Quer, ... Journal on Satisfiability, Boolean Modeling and Computation 9 (1), 135-172, 2014 | 35 | 2014 |
| Test of reconfigurable modules in scan networks R Cantoro, FG Zadegan, M Palena, P Pasini, E Larsson, MS Reorda IEEE Transactions on Computers 67 (12), 1806-1817, 2018 | 19 | 2018 |
| Test time minimization in reconfigurable scan networks R Cantoro, M Palena, P Pasini, MS Reorda 2016 IEEE 25th Asian Test Symposium (ATS), 119-124, 2016 | 19 | 2016 |
| Interpolation with guided refinement: Revisiting incrementality in sat-based unbounded model checking G Cabodi, M Palena, P Pasini 2014 Formal Methods in Computer-Aided Design (FMCAD), 43-50, 2014 | 18 | 2014 |
| Fast cone-of-influence computation and estimation in problems with multiple properties C Loiacono, M Palena, P Pasini, D Patti, S Quer, S Ricossa, ... 2013 Design, Automation & Test in Europe Conference & Exhibition (DATE), 803-806, 2013 | 15 | 2013 |
| A 7/2-approximation algorithm for the maximum duo-preservation string mapping problem N Boria, G Cabodi, P Camurati, M Palena, P Pasini, S Quer 27th Annual Symposium on Combinatorial Pattern Matching (CPM 2016), 2016 | 12 | 2016 |
| To split or to group: from divide-and-conquer to sub-task sharing for verifying multiple properties in model checking G Cabodi, PE Camurati, C Loiacono, M Palena, P Pasini, D Patti, S Quer International Journal on Software Tools for Technology Transfer 20, 313-325, 2018 | 11 | 2018 |
| SAT solver management strategies in IC3: an experimental approach G Cabodi, PE Camurati, A Mishchenko, M Palena, P Pasini Formal Methods in System Design 50, 39-74, 2017 | 7 | 2017 |
| Optimizing binary decision diagrams for interpretable machine learning classification G Cabodi, PE Camurati, J Marques-Silva, M Palena, P Pasini IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2024 | 6 | 2024 |
| Interpolation-based learning as a mean to speed-up bounded model checking (short paper) G Cabodi, P Camurati, M Palena, P Pasini, D Vendraminetto Software Engineering and Formal Methods: 15th International Conference, SEFM …, 2017 | 5 | 2017 |
| Reducing interpolant circuit size by ad-hoc logic synthesis and SAT-based weakening G Cabodi, PE Camurati, M Palena, P Pasini, D Vendraminetto 2016 Formal Methods in Computer-Aided Design (FMCAD), 25-32, 2016 | 4 | 2016 |
| To split or to group: from divide-and-conquer to sub-task sharing in verifying multiple properties P Camurati, C Loiacono, P Pasini, D Patti, S Quer International Workshop on Design and Implementation of Formal Tools and …, 2014 | 4 | 2014 |
| Interpolation with guided refinement: revisiting incrementality in SAT-based unbounded model checking G Cabodi, PE Camurati, M Palena, P Pasini Formal Methods in System Design 60 (2), 117-146, 2022 | 3 | 2022 |
| Schema-based instruction with enumerative combinatorics and recursion to develop computer engineering students' problem-solving skills G Cabodi, P Camurati, P Pasini, D Patti, D Vendraminetto International Journal of Engineering Education 36 (5), 1505-1528, 2020 | 2 | 2020 |
| Reducing interpolant circuit size through SAT-based weakening G Cabodi, PE Camurati, M Palena, P Pasini, D Vendraminetto IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2019 | 2 | 2019 |
| A Greedy Approach to Answer Reachability Queries on DAGs N Boria, G Cabodi, P Camurati, M Palena, P Pasini, S Quer arXiv preprint arXiv:1611.02506, 2016 | 2 | 2016 |
| Logic synthesis for interpolant circuit compaction G Cabodi, PE Camurati, M Palena, P Pasini, D Vendraminetto IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2018 | 1 | 2018 |
| Improving bit-level model checking algorithms for scalability through circuit-based reasoning P Pasini Politecnico di Torino, 2017 | 1 | 2017 |
| Dal problema al programma. Introduzione al problem-solving in linguaggio C G Cabodi, P Pasini Maggioli Editore, 2016 | 1 | 2016 |
| Ricorsione e problem-solving. Strategie algoritmiche in linguaggio C G Cabodi, PE Camurati, P Pasini, D Patti, D Vendraminetto Maggioli Editore, 2015 | 1 | 2015 |
Danilo VendraminettoPost-doc Researcher, Politecnico di TorinoVerified email at polito.it
