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Daniel W. Chang
Daniel W. Chang
Associate Professor of Electrical and Computer Engineering, Rose-Hulman Institute of Technology
Verified email at rose-hulman.edu
Title
Cited by
Cited by
Year
ERCBench: An open-source benchmark suite for embedded and reconfigurable computing
DW Chang, CD Jenkins, PC Garcia, SZ Gilani, P Aguilera, A Nagarajan, ...
Field Programmable Logic and Applications (FPL), 2010 International …, 2010
472010
Reevaluating the latency claims of 3D stacked memories
DW Chang, G Byun, H Kim, M Ahn, S Ryu, NS Kim, MJ Schulte
ASP-DAC, 657-662, 2013
312013
From LEGO to Arduino: Enhancement of ECE freshman design with practical applications
CA Berry, D Chang, C Miller
2016 ASEE Annual Conference & Exposition, 2016
112016
Dynamic bandwidth scaling for embedded DSPs with 3D-stacked DRAM and wide I/Os
DW Chang, YH Son, JH Ahn, H Kim, M Ahn, MJ Schulte, NS Kim
2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 747-754, 2013
52013
Analyzing the performance and energy impact of 3D memory integration on embedded DSPs
DW Chang, NS Kim, MJ Schulte
2011 International Conference on Embedded Computer Systems: Architectures …, 2011
32011
Apparatus and method for adjusting bandwidth
HY Kim, NS Kim, DW Chang
US Patent 9,588,570, 2017
22017
Studying Victim Caches in GPUs
EM Taylor, DW Chang
Parallel, Distributed and Network-based Processing (PDP), 2018 26th …, 2018
12018
Improving Student Confidence and Retention using an Introductory Computer Engineering Course
DW Chang
ASEE Annual Conference & Exposition, 2017
12017
A quantitative analysis of the performance of computing architectures used in neural simulations
MS K. Daruwalla, N. Olivero, A. Pluger, S. Rao, D.W. Chang
Journal of Neuroscience Methods 311, 57-66, 2018
2018
From LEGO to Arduino: Enhancement of ECE Freshman Design with Practical Applications
D Chang, C Berry, C Miller
ASEE Annual Conference & Exposition, 2016
2016
3D Stacked Memories for Digital Signal Processors
DW Chang
The University of Wisconsin-Madison, 2013
2013
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