| Intermediate fabrics: Virtual architectures for circuit portability and fast placement and routing J Coole, G Stitt Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware …, 2010 | 138 | 2010 |
| Intermediate fabrics: Virtual architectures for near-instant FPGA compilation G Stitt, J Coole IEEE Embedded Systems Letters 3 (3), 81-84, 2011 | 62 | 2011 |
| Fast, flexible high-level synthesis from OpenCL using reconfiguration contexts J Coole, G Stitt IEEE Micro 34 (1), 42-53, 2013 | 43 | 2013 |
| Adjustable-cost overlays for runtime compilation J Coole, G Stitt 2015 IEEE 23rd Annual International Symposium on Field-Programmable Custom …, 2015 | 42 | 2015 |
| CSP hybrid space computing for STP-H5/ISEM on ISS C Wilson, J Stewart, P Gauvin, J MacKinnon, J Coole, J Urriste, A George, ... | 29 | 2015 |
| BPR: fast FPGA placement and routing using macroblocks J Coole, G Stitt Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware …, 2012 | 26 | 2012 |
| Overlay architecture for programming FPGAs JR Coole, GM Stitt US Patent 10,516,396, 2019 | 22 | 2019 |
| A traversal cache framework for fpga acceleration of pointer data structures: A case study on barnes-hut n-body simulation J Coole, J Wernsing, G Stitt 2009 International Conference on Reconfigurable Computing and FPGAs, 143-148, 2009 | 18 | 2009 |
| Traversal caches: A first step towards FPGA acceleration of pointer-based data structures G Stitt, G Chaudhari, J Coole Proceedings of the 6th IEEE/ACM/IFIP international conference on Hardware …, 2008 | 17 | 2008 |
| Developing dynamic profiling and debugging support in OpenCL for FPGAs A Verma, H Zhou, S Booth, R King, J Coole, A Keep, J Marshall, W Feng Proceedings of the 54th Annual Design Automation Conference 2017, 1-6, 2017 | 16 | 2017 |
| An end-to-end tool flow for fpga-accelerated scientific computing G Stitt, A George, H Lam, M Smith, V Aggarwal, G Wang, C Reardon, ... IEEE Design & Test of Computers 28 (4), 68-77, 2011 | 9 | 2011 |
| Traversal caches: a framework for FPGA acceleration of pointer data structures J Coole, G Stitt International Journal of Reconfigurable Computing 2010 (1), 652620, 2010 | 8 | 2010 |
| A recurrently generated overlay architecture for rapid FPGA application development D Wilson, G Stitt, J Coole Proceedings of the 9th International Symposium on Highly-Efficient …, 2018 | 4 | 2018 |
| Implementing configurable packet parsers for field-programmable gate arrays using hardened resources J Coole US Patent 11,095,760, 2021 | 3 | 2021 |
| Jason Anderson, University of Toronto David Andrews, University of Arkansas Kubilay Atasu, IBM Research-Zurich Kia Bazargan, Univ of Minnesota J Becker, M Blott, C Bobda, G Botella, C Bouganis, E Bozorgzadeh, ... | | |
| Kermin Fleming (Intel) A Dehon, A Koch, A Schmidt, B Rouhani, B Hutchings, C Plessl, C Bobda, ... | | |
