| Structure and process of basic complementary logic gate made by junctionless transistors SS Chung, ER Hsieh US Patent App. 13/064,168, 2012 | 148 | 2012 |
| IEDM Tech. Dig. SW Chang IEDM Tech. Dig, 417-420, 2013 | 118 | 2013 |
| Demonstration of 3D vertical RRAM with ultra low-leakage, high-selectivity and self-compliance memory cells Q Luo, X Xu, H Liu, H Lv, T Gong, S Long, Q Liu, H Sun, W Banerjee, L Li, ... 2015 IEEE International Electron Devices Meeting (IEDM), 10.2. 1-10.2. 4, 2015 | 99 | 2015 |
| Integration of 4F2 selector-less crossbar array 2Mb ReRAM based on transition metal oxides for high density memory applications HD Lee, SG Kim, K Cho, H Hwang, H Choi, J Lee, SH Lee, HJ Lee, J Suh, ... 2012 Symposium on VLSI Technology (VLSIT), 151-152, 2012 | 75 | 2012 |
| A new approach to determine the effective channel length and the drain-and-source series resistance of miniaturized MOSFET's JC Guo, SSS Chung, CCH Hsu IEEE Transactions on Electron Devices 41 (10), 1811-1818, 1994 | 75 | 1994 |
| The Understanding of Resistive Switching Mechansim in HfO2-Based Resistive Random Access Memory JP Wang, SS Chung, HY Lee, PS Chen, YS Chen, FT Chen, PY Gu, ... IEDM, 2011 | 73 | 2011 |
| The observation of trapping and detrapping effects in high-k gate dielectric MOSFETs by a new gate current random telegraph noise (IG-RTN) approach CM Chang, SS Chung, YS Hsieh, LW Cheng, CT Tsai, GH Ma, SC Chien, ... 2008 IEEE International Electron Devices Meeting, 1-4, 2008 | 69 | 2008 |
| An analytical threshold-voltage model of trench-isolated MOS devices with nonuniformly doped substrates SSS Chung, TC Li IEEE Transactions on Electron Devices 39 (3), 614-622, 1992 | 64 | 1992 |
| Fully CMOS compatible 3D vertical RRAM with self-aligned self-selective cell enabling sub-5nm scaling X Xu, Q Luo, T Gong, H Lv, S Long, Q Liu, SS Chung, J Li, M Liu 2016 IEEE Symposium on VLSI Technology, 1-2, 2016 | 63 | 2016 |
| A new method for characterizing the spatial distributions of interface states and oxide-trapped charges in LDD n-MOSFETs RGH Lee, JS Su, SS Chung IEEE Transactions on Electron Devices 43 (1), 81-89, 1996 | 61 | 1996 |
| Method of making a body contact for a MOSFET device fabricated in an SOI layer CH Hsu, SC Wong, MS Liang, SS Chung US Patent 5,573,961, 1996 | 56 | 1996 |
| A new approach to determine the drain-and-source series resistance of LDD MOSFET's SSS Chung, JS Lee IEEE Transactions on Electron Devices 40 (9), 1709-1711, 1993 | 52 | 1993 |
| A novel and direct determination of the interface traps in sub-100 nm CMOS devices with direct tunneling regime (12/spl sim/16 A) gate oxide SS Chung, SJ Chen, CK Yang, SM Cheng, SH Lin, YC Sheng, HS Lin, ... 2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No …, 2002 | 49 | 2002 |
| Effects of hot carrier induced interface state generation in submicron LDD MOSFET's T Wang, C Huang, PC Chou, SSS Chung, TE Chang IEEE transactions on electron devices 41 (9), 1618-1622, 1994 | 45 | 1994 |
| A novel leakage current separation technique in a direct tunneling regime gate oxide SONOS memory cell SS Chung, PY Chiang, G Chou, CT Huang, P Chen, CH Chu, CCH Hsu IEEE International Electron Devices Meeting 2003, 26.6. 1-26.6. 4, 2003 | 44 | 2003 |
| A unified approach to profiling the lateral distributions of both oxide charge and interface states in n-MOSFET's under various bias stress conditions SM Cheng, CM Yih, JC Yeh, SN Kuo, SS Chung IEEE Transactions on Electron Devices 44 (11), 1908-1914, 1997 | 44 | 1997 |
| Body contact for a MOSFET device fabricated in an SOI layer CH Hsu, SC Wong, MS Liang, SS Chung US Patent 5,818,085, 1998 | 43 | 1998 |
| Performance and reliability evaluations of p-channel flash memories with different programming schemes SS Chung, SN Kuo, CM Yih, TS Chao International Electron Devices Meeting. IEDM Technical Digest, 295-298, 1997 | 36 | 1997 |
| An efficient semi-empirical model of the IV characteristics for LDD MOSFETS SSS Chung, TS Lin, YG Chen IEEE transactions on electron devices 36 (9), 1691-1702, 1989 | 33 | 1989 |
| A new approach to simulating n-MOSFET gate current degradation by including hot-electron induced oxide damage CM Yih, SM Cheng, SS Chung IEEE Transactions on Electron Devices 45 (11), 2343-2348, 1998 | 32 | 1998 |
Qing LuoInstitute of Microelectronics, Chinese Academy of Sciences在 ime.ac.cn 的電子郵件地址已通過驗證
