| Gate leakage reduction for scaled devices using transistor stacking S Mukhopadhyay, C Neau, RT Cakici, A Agarwal, CH Kim, K Roy | 218 | 2003 |
| Modeling and Circuit Synthesis for Independently Controlled Double Gate FinFET Devices A Datta, A Goel, RT Cakici, H Mahmoodi, D Lekshmanan, K Roy | 117 | 2007 |
| Double-gate SOI devices for low-power and high-performance applications K Roy, H Mahmoodi, S Mukhopadhyay, H Ananthan, A Bansal, T Cakici ICCAD-2005. IEEE/ACM International Conference on Computer-Aided Design, 2005 …, 2005 | 93 | 2005 |
| Analysis of options in double-gate MOS technology: A circuit perspective RT Cakici, K Roy IEEE transactions on electron devices 54 (12), 3361-3368, 2007 | 47 | 2007 |
| FinFET based SRAM design for low standby power applications T Cakici, K Kim, K Roy 8th International Symposium on Quality Electronic Design (ISQED'07), 127-132, 2007 | 47 | 2007 |
| A low power four transistor Schmitt Trigger for asymmetric double gate fully depleted SOI devices Cakici, Bansal, Roy 2003 IEEE International Conference on SOI, 21-22, 2003 | 45 | 2003 |
| Independent gate skewed logic in double-gate SOI technology T Cakici, H Mahmoodi, S Mukhopadhyay, K Roy 2005 IEEE International SOI Conference Proceedings, 83-84, 2005 | 19 | 2005 |
| Device Characteristics and Equivalent Circuits for NMOS Gate-to-Drain Soft and Hard Breakdown in Polysilicon/SiON Gate Stacks PE Nicollian, RT Cakici, AT Krishnan, VK Reddy, A Seshadri | 12 | 2011 |
| Process Tolerant ß-ratio Modulation for Ultra-Dynamic Voltage Scaling ME Hwang, T Cakici, K Roy 2007 Design, Automation & Test in Europe Conference & Exhibition, 1-6, 2007 | 9 | 2007 |
| High Q and high tuning range FinFET based varactors for low cost SoC integration T Cakici, B Jung, K Roy 2006 IEEE international SOI Conferencee Proceedings, 67-68, 2006 | 3 | 2006 |
| Current mirror evaluation logic: A new circuit style for high fan-in dynamic gates T Cakici, K Roy Proceedings of the 28th European Solid-State Circuits Conference, 395-398, 2002 | 2 | 2002 |
| SPICE simulations of data path timing margins after dielectric breakdown from gate-to-drain using accurate equivalent circuit models RT Cakici, PE Nicollian, CA Chancellor | 1 | 2012 |
| System and circuit for simulating gate-to-drain breakdown PE Nicollian, RT Cakici US Patent 8,554,531, 2013 | | 2013 |
| Exploiting independent gate technology in Multiple-Gate silicon CMOS circuit design T Cakici Purdue University, 2007 | | 2007 |
Kaushik RoyProfessor of Electrical and Computer Engineering, Purdue UniversityVerified email at purdue.edu
