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Masato Tamura
Masato Tamura
Hitachi America, Ltd.
Verified email at hal.hitachi.com - Homepage
Title
Cited by
Cited by
Year
Qpic: Query-based pairwise human-object interaction detection with image-wide contextual information
M Tamura, H Ohashi, T Yoshinaga
Proceedings of the IEEE/CVF Conference on Computer Vision and Pattern …, 2021
1662021
Omnidirectional pedestrian detection by rotation invariant training
M Tamura, S Horiguchi, T Murakami
2019 IEEE winter conference on applications of computer vision (WACV), 1989-1998, 2019
462019
Augmented hard example mining for generalizable person re-identification
M Tamura, T Murakami
arXiv preprint arXiv:1910.05280, 2019
222019
Hunting group clues with transformers for social group activity recognition
M Tamura, R Vishwakarma, R Vennelakanti
European Conference on Computer Vision, 19-35, 2022
132022
1.68 μJ/signature-generation 256-bit ECDSA over GF (p) signature generator for IoT devices
M Tamura, M Ikeda
2016 IEEE Asian Solid-State Circuits Conference (A-SSCC), 341-344, 2016
122016
Montgomery multiplier design for ECDSA signature generation processor
M Tamura, M Ikeda
IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and …, 2016
62016
BCaR: Beginner Classifier as Regularization Towards Generalizable Re-ID
M Tamura, T Yoshinaga
2020 The British Machine Vision Conference (BMVC), 2020
42020
Object search device and object search method
M Tamura, T Yoshinaga, A Hiroike, H Nakamae, Y Yanashima
US Patent App. 17/784,472, 2023
22023
Optimal design on asynchronous system with gate-level pipelining
M Tamura, A Ito, M Ikeda
2015 IEEE 11th International Conference on ASIC (ASICON), 1-4, 2015
22015
Random Word Data Augmentation with CLIP for Zero-Shot Anomaly Detection
M Tamura
arXiv preprint arXiv:2308.11119, 2023
2023
Segmentation-based bounding box generation for omnidirectional pedestrian detection
M Tamura, T Yoshinaga
The Visual Computer, 1-12, 2023
2023
Video analysis system and video analysis method
T Tarui, T Murakami, S Fukuda, M Tamura, K Hiroki
US Patent App. 17/143,638, 2021
2021
Implementation of ECDSA Using Gate-level Pipelined Self-synchronous Circuit
M Tamura, M Ikeda
IEICE Technical Report; IEICE Tech. Rep. 115 (338), 7-12, 2015
2015
SOTB 65nm CMOS Design of Gate-Level Dual Pipeline Self-Synchronous Wallace Tree Multiplier
M Tamura, M Ikeda
IEICE Technical Report; IEICE Tech. Rep. 114 (59), 39-44, 2014
2014
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