| Neural network based attack on a masked implementation of AES R Gilmore, N Hanley, M O'Neill 2015 IEEE International Symposium on Hardware Oriented Security and Trust …, 2015 | 160 | 2015 |
| FPGA implementations of the round two SHA-3 candidates B Baldwin, A Byrne, L Lu, M Hamilton, N Hanley, M O'Neill, WP Marnane 2010 International Conference on Field Programmable Logic and Applications …, 2010 | 130 | 2010 |
| Hardware comparison of the ISO/IEC 29192-2 block ciphers N Hanley, M ONeill 2012 IEEE Computer Society Annual Symposium on VLSI, 57-62, 2012 | 97 | 2012 |
| A machine learning attack resistant multi-PUF design on FPGA Q Ma, C Gu, N Hanley, C Wang, W Liu, M O'Neill 2018 23rd Asia and South Pacific Design Automation Conference (ASP-DAC), 97-104, 2018 | 77 | 2018 |
| Improved reliability of FPGA-based PUF identification generator design C Gu, N Hanley, M O'neill ACM Transactions on Reconfigurable Technology and Systems (TRETS) 10 (3), 1-23, 2017 | 65 | 2017 |
| Exploiting collisions in addition chain-based exponentiation algorithms using a single trace N Hanley, HS Kim, M Tunstall Topics in Cryptology–-CT-RSA 2015: The Cryptographer's Track at the RSA …, 2015 | 62 | 2015 |
| Exploiting collisions in addition chain-based exponentiation algorithms using a single trace N Hanley, HS Kim, M Tunstall Topics in Cryptology–-CT-RSA 2015: The Cryptographer's Track at the RSA …, 2015 | 62 | 2015 |
| Evaluation of large integer multiplication methods on hardware C Rafferty, M O’Neill, N Hanley IEEE Transactions on Computers 66 (8), 1369-1382, 2017 | 58 | 2017 |
| Large scale RO PUF analysis over slice type, evaluation time and temperature on 28nm Xilinx FPGAs R Hesselbarth, F Wilde, C Gu, N Hanley 2018 IEEE International Symposium on Hardware Oriented Security and Trust …, 2018 | 49 | 2018 |
| A flip-flop based arbiter physical unclonable function (APUF) design with high entropy and uniqueness for FPGA implementation C Gu, W Liu, Y Cui, N Hanley, MÁ O’Neill, F Lombardi IEEE Transactions on Emerging Topics in Computing 9 (4), 1853-1866, 2019 | 47 | 2019 |
| Unknown plaintext template attacks N Hanley, M Tunstall, WP Marnane Information Security Applications: 10th International Workshop, WISA 2009 …, 2009 | 46 | 2009 |
| High-speed fully homomorphic encryption over the integers X Cao, C Moore, M O’Neill, N Hanley, E O’Sullivan Financial Cryptography and Data Security: FC 2014 Workshops, BITCOIN and …, 2014 | 45 | 2014 |
| Accelerating fully homomorphic encryption over the integers with super-size hardware multiplier and modular reduction X Cao, C Moore, M O’Neill, E O’Sullivan, N Hanley Cryptology ePrint Archive, 2013 | 42 | 2013 |
| Optimised multiplication architectures for accelerating fully homomorphic encryption X Cao, C Moore, M O'Neill, E O'Sullivan, N Hanley IEEE Transactions on Computers 65 (9), 2794-2806, 2015 | 39 | 2015 |
| Fpga implementations of sha-3 candidates: cubehash, grøstl, lane, shabal and spectral hash B Baldwin, A Byrne, M Hamilton, N Hanley, RP McEvoy, W Pan, ... 2009 12th Euromicro Conference on Digital System Design, Architectures …, 2009 | 37 | 2009 |
| Fpga implementations of sha-3 candidates: cubehash, grøstl, lane, shabal and spectral hash B Baldwin, A Byrne, M Hamilton, N Hanley, RP McEvoy, W Pan, ... 2009 12th Euromicro Conference on Digital System Design, Architectures …, 2009 | 37 | 2009 |
| Novel lightweight FF-APUF design for FPGA C Gu, Y Cui, N Hanley, M O'Neill 2016 29th IEEE International System-on-Chip Conference (SOCC), 75-80, 2016 | 34 | 2016 |
| Correlation power analysis of large word sizes M Tunstall, N Hanley, RP McEvoy, C Whelan, CC Murphy, WP Marnane IET Irish Signals and Systems Conference (ISSC), 145-150, 2007 | 34 | 2007 |
| Targeting FPGA DSP slices for a large integer multiplier for integer based FHE C Moore, N Hanley, J McAllister, M O’Neill, E O’Sullivan, X Cao Financial Cryptography and Data Security: FC 2013 Workshops, USEC and WAHC …, 2013 | 32 | 2013 |
| A hardware wrapper for the SHA-3 hash algorithms B Baldwin, A Byrne, L Lu, M Hamilton, N Hanley, M O'Neill, WP Marnane IET Irish Signals and Systems Conference (ISSC 2010), 1-6, 2010 | 31 | 2010 |
