| Characterization and optimization of inverted-T FinFET under nanoscale dimensions E Yu, K Heo, S Cho IEEE Transactions on Electron Devices 65 (8), 3521-3527, 2018 | 42 | 2018 |
| Fabrication and characterization of a thin-body poly-Si 1T DRAM with charge-trap effect JH Seo, YJ Yoon, E Yu, W Sun, H Shin, IM Kang, JH Lee, S Cho IEEE Electron Device Letters 40 (4), 566-569, 2019 | 34 | 2019 |
| A band-engineered one-transistor DRAM with improved data retention and power efficiency E Yu, S Cho, H Shin, BG Park IEEE Electron Device Letters 40 (4), 562-565, 2019 | 24 | 2019 |
| Ultrathin sige shell channel p-type finfet on bulk si for sub-10-nm technology nodes E Yu, WJ Lee, J Jung, S Cho IEEE Transactions on Electron Devices 65 (4), 1290-1297, 2018 | 24 | 2018 |
| Pd/IGZO/p+-Si Synaptic Device with Self-Graded Oxygen Concentrations for Highly Linear Weight Adjustability and Improved Energy Efficiency D Kim, JT Jang, E Yu, J Park, J Min, DM Kim, SJ Choi, HS Mo, S Cho, ... ACS Applied Electronic Materials 2 (8), 2390-2397, 2020 | 20 | 2020 |
| Design and characterization of semi-floating-gate synaptic transistor Y Cho, JY Lee, E Yu, JH Han, MH Baek, S Cho, BG Park Micromachines 10 (1), 32, 2019 | 15 | 2019 |
| A quantum-well charge-trap synaptic transistor with highly linear weight tunability E Yu, S Cho, K Roy, BG Park IEEE Journal of the Electron Devices Society 8, 834-840, 2020 | 14 | 2020 |
| Design and analysis of nanowire p-type MOSFET coaxially having silicon core and germanium peripheral channel E Yu, S Cho Japanese Journal of Applied Physics 55 (11), 114001, 2016 | 11 | 2016 |
| A silicon-compatible synaptic transistor capable of multiple synaptic weights toward energy-efficient neuromorphic systems E Yu, S Cho, BG Park Electronics 8 (10), 1102, 2019 | 10 | 2019 |
| Multi-level neuromorphic devices built on emerging ferroic materials: A review C Wang, A Agrawal, E Yu, K Roy Frontiers in Neuroscience 15, 661667, 2021 | 8 | 2021 |
| Processing and characterization of ultra-thin poly-crystalline silicon for memory and logic applications E Yu, Y Kim, J Lee, Y Cho, WJ Lee, S Cho Journal of Semiconductor Technology and Science 18 (2), 172-179, 2018 | 7 | 2018 |
| Ferroelectric FET based coupled-oscillatory network for edge detection E Yu, A Agrawal, D Zheng, M Si, M Koo, DY Peide, SK Gupta, K Roy IEEE Electron Device Letters 42 (11), 1670-1673, 2021 | 5 | 2021 |
| Interfacial layer engineering in sub-5-nm HZO: Enabling low-temperature process, low-voltage operation, and high robustness E Yu, X Lyu, M Si, DY Peide, K Roy IEEE Transactions on Electron Devices, 2023 | 4 | 2023 |
| A Highly Scalable and Energy-Efficient 1T DRAM Embedding a SiGe Quantum Well Structure for Significant Retention Enhancement E Yu, S Cho 2018 International Conference on Simulation of Semiconductor Processes and …, 2018 | 3 | 2018 |
| An accurate simulation study on capacitance-voltage characteristics of metal-oxide-semiconductor field-effect transistors in novel structures E Yu, S Cho, BG Park Physica B: Condensed Matter 521, 305-311, 2017 | 2 | 2017 |
| One-transistor DRAM cell device having quantum well structure S Cho, E Yu, JY Lee US Patent 11,158,732, 2021 | 1 | 2021 |
| Si‐core/SiGe‐shell channel nanowire FET for sub‐10‐nm logic technology in the THz regime E Yu, B Son, B Kam, YS Joh, S Park, WJ Lee, J Jung, S Cho ETRI journal 41 (6), 829-837, 2019 | 1 | 2019 |
| SiGe Heterojunction FinFET Towards Tera-Hertz Applications E Yu, WJ Lee, J Jung, S Cho Journal of the Korean Physical Society 72, 527-532, 2018 | 1 | 2018 |
| Ferroelectric capacitors and field-effect transistors as in-memory computing elements for machine learning workloads E Yu, GK K, U Saxena, K Roy Scientific Reports 14 (1), 9426, 2024 | | 2024 |
| Fabrication method of semiconductor device having SIGe shell channel and semiconductor device fabricated by the same S Cho, E Yu US Patent 10,991,813, 2021 | | 2021 |
Seongjae ChoDepartment of Electronic and Electrical Engineering, Ewha Womans UniversityVerified email at ewha.ac.kr
