| A scalable processing-in-memory accelerator for parallel graph processing J Ahn, S Hong, S Yoo, O Mutlu, K Choi International Symposium on Computer Architecture, 105-117, 2015 | 979 | 2015 |
| PaLM 2 technical report R Anil, AM Dai, O Firat, M Johnson, D Lepikhin, A Passos, S Shakeri, ... arXiv preprint arXiv:2305.10403, 2023 | 765 | 2023 |
| PIM-enabled instructions: A low-overhead, locality-aware processing-in-memory architecture J Ahn, S Yoo, O Mutlu, K Choi International Symposium on Computer Architecture, 336-348, 2015 | 600 | 2015 |
| Gemini: A family of highly capable multimodal models G Team arXiv preprint arXiv:2312.11805, 2023 | 419 | 2023 |
| Weighted-entropy-based quantization for deep neural networks E Park, J Ahn, S Yoo Conference on Computer Vision and Pattern Recognition, 2017 | 295 | 2017 |
| Software-defined far memory in warehouse-scale computers A Lagar-Cavilla, J Ahn, S Souhlal, N Agarwal, R Burny, S Butt, J Chang, ... International Conference on Architectural Support for Programming Languages …, 2019 | 134 | 2019 |
| ZeNA: Zero-aware neural network accelerator D Kim, J Ahn, S Yoo IEEE Design & Test 35 (1), 39-46, 2018 | 126 | 2018 |
| DASCA: Dead write prediction assisted STT-RAM cache architecture J Ahn, S Yoo, K Choi International Symposium on High Performance Computer Architecture, 25-36, 2014 | 119 | 2014 |
| Making DRAM stronger against row hammering M Son, H Park, J Ahn, S Yoo Design Automation Conference, 55:1-55:6, 2017 | 108 | 2017 |
| A novel zero weight/activation-aware hardware architecture of convolutional neural network D Kim, J Ahn, S Yoo Design, Automation & Test in Europe Conference, 1462-1467, 2017 | 79 | 2017 |
| An imitation learning approach for cache replacement EZ Liu, M Hashemi, K Swersky, P Ranganathan, J Ahn International Conference on Machine Learning, 2020 | 75 | 2020 |
| Semiconductor memory device including non-volatile memory, cache memory, and computer system S Kim, H Kwon, Y Kwon, K Choi, J Ahn US Patent 9,250,997, 2016 | 74 | 2016 |
| Zero and data reuse-aware fast convolution for deep neural networks on GPU H Park, D Kim, J Ahn, S Yoo International Conference on Hardware/Software Codesign and System Synthesis …, 2016 | 60 | 2016 |
| Prediction hybrid cache: An energy-efficient STT-RAM cache architecture J Ahn, S Yoo, K Choi IEEE Transactions on Computers 65 (3), 940-951, 2016 | 54 | 2016 |
| Power-efficient predication techniques for acceleration of control flow execution on CGRA K Han, J Ahn, K Choi ACM Transactions on Architecture and Code Optimization 10 (2), 8:1-8:25, 2013 | 43 | 2013 |
| Write intensity prediction for energy-efficient non-volatile caches J Ahn, S Yoo, K Choi International Symposium on Low Power Electronics and Design, 223-228, 2013 | 38 | 2013 |
| Lower-bits cache for low power STT-RAM caches J Ahn, K Choi International Symposium on Circuits and Systems, 480-483, 2012 | 33 | 2012 |
| Dynamic power management of off-chip links for hybrid memory cubes J Ahn, S Yoo, K Choi Design Automation Conference, 1-6, 2014 | 27 | 2014 |
| Method and apparatus for processing instructions using processing-in-memory K Choi, J Ahn, S Yoo US Patent 10,860,323, 2020 | 24 | 2020 |
| Energy-efficient exclusive last-level hybrid caches consisting of SRAM and STT-RAM N Kim, J Ahn, W Seo, K Choi International Conference on Very Large Scale Integration, 183-188, 2015 | 18 | 2015 |
Sungjoo YooSeoul National UniversityVerified email at snu.ac.kr
