| Implementation of Vedic multiplier for digital signal processing SS Kerur, JCN Prakash Narchi, HM Kittur, VA Girish International Conference on VLSI, Communication & Instrumentation (ICVCI), 1-6, 2011 | 108 | 2011 |
| Low power high speed 16x16 bit multiplier using vedic mathematics RK Bathija, RS Meena, S Sarkar, R Sahu International Journal of Computer Applications 59 (6), 2012 | 56 | 2012 |
| A high speed 16* 16 multiplier based on Urdhva Tiryakbhyam Sutra BR Raju, DV Satish International Journal of Science Engineering and Advance Technology, IJSEAT …, 2013 | 16 | 2013 |
| Implementation of Vedic multiplier in image compression using DCT algorithm SS Kerur, P Narchi, HM Kittur, VA Girish 2014 2nd international conference on devices, circuits and systems (ICDCS), 1-6, 2014 | 14 | 2014 |
| Design and simulation of low power successive approximation register for A/D converters using 0.18 um CMOS technology KN Hosur, GV Attimarad, HM Kittur, SS Kerur International Journal of Engineering and Technology (IJET) 9, 2016 | 9 | 2016 |
| Design and Simulation of Floating Point Pipelined ALU Using HDL and IP Core Generator P Itagi Mahi, SS Kerur ISSN 2277–4106© 2013 INPRESSCO, 2013 | 5 | 2013 |
| FPGA-Based Implementation of Digital Filters for Image Denoising SK Shirakol, V Hiremath, SS Kerur Smart Sensors Measurements and Instrumentation: Select Proceedings of CISCON …, 2021 | 2 | 2021 |
| Design of a High Speed Multiplier by Using Ancient Vedic Mathematics Approach for Digital Arithmetic A Kumar, S Kamya International Journal of Electrical and Electronics Engineers 8 (2), 244-255, 2016 | 2 | 2016 |
| Architectural Design and Optimization of Distributed Arithmetic based 2-D Discrete Cosine Transform S Shirakol, SS Kerur ICTACT Journal on Microelectronics 8 (01), 1275-1282, 2022 | 1 | 2022 |
| An Area-Efficient JK Flip-Flop-Based Phase Detector for Phase Measurement System Based on FPGA SS Kerur, Veeresh, SK Shirakol Innovations in Electronics and Communication Engineering: Proceedings of the …, 2022 | 1 | 2022 |
| Hardware Implementation and Comparison of OE Routing Algorithm with Extended XY Routing Algorithm for 2D Mesh on Network on Chip R Velangi, SS Kerur International Conference on Micro-Electronics and Telecommunication …, 2021 | 1 | 2021 |
| Design and Analysis of 10-bit, 2 MS/s SAR ADC Using Nonredundant SAR and Split DAC KN Hosur, GV Attimarad, HM Kittur, GG Mane, SS Kerur Proceeding of the Second International Conference on Microelectronics …, 2019 | 1 | 2019 |
| An Improved VLSI Architectural Design of Discrete Cosine Transform Based on the Loeffler-DCT Algorithm. S Shirakol, SS Kerur International Journal of Intelligent Engineering & Systems 16 (5), 2023 | | 2023 |
| Industry Linked Projects as Tools for Improving Employability of Budding Engineers SS Navalgund, JC Nidagundi, SS Kerur Journal of Engineering Education Transformations, 55-63, 2021 | | 2021 |
| Machine Learning-Based Implementation of Image Corner Detection Using SVM Algorithm for Biomedical Applications SM Herur, SS Kerur, HC Hadimani Nanoelectronics, Circuits and Communication Systems: Proceeding of NCCS 2019 …, 2021 | | 2021 |
| Neural Network Based Implementation of Corner Detection for Biomedical Application in Computer Vision. SM Herur, SS Kerur, KN Hosur Indian Journal of Public Health Research & Development 11 (3), 2020 | | 2020 |
| Booth Modified RNS Multiplier in RNS to Binary Code Converator Using {2P+ 1 2P, 2p-1} SS Kerur, H Kittu MR International Journal of Engineering & Technology 6 (2), 27-31, 2018 | | 2018 |
| DESIGN AND SYNTHESIS OF VEDIC FLOATING POINT MULTIPLIER S Gulannanavar, SS Kerur International Journal of Research in Management & Social Science, 77, 2017 | | 2017 |
| Digital Implementation of Efficient Low-Power and Compact Codec System for Portable Devices Using CADENCE Tool YK Udara, PS Bellerimath, GG Mane, SS Kerur | | 2016 |
| Design of High Gain two Stage Amplifier for ADC Applications Using Cadence 180nm Technology YK Udara, PS Bellerimath, GG Mane, SS Kerur | | 2016 |
