| A Novel 8T Cell-Based Subthreshold Static RAM for Ultra-Low Power Platform Applications T Kim, S Manisankar, Y Chung Electronics 9 (6), 1-17, 2020 | 7 | 2020 |
| P‐channel logic 2 T eDRAM macro with high retention bit architecture S Manisankar, Y Chung International Journal of Circuit Theory and Applications 46 (7), 1416-1425, 2018 | 4 | 2018 |
| Read disturb-free SRAM bit-cell for subthreshold memory applications H Kim, T Kim, S Manisankar, Y Chung 2017 International Conference on Electron Devices and Solid-State Circuits …, 2017 | 3 | 2017 |
| Experimental N-style two-transistor eDRAM in logic CMOS technology H Das, S Manisankar, W Cheng, Y Chung 2015 IEEE International Conference on Electron Devices and Solid-State …, 2015 | 1 | 2015 |
| Low Quiescent Current High Performance Capacitor-free LDO Regulator with Optimal Power using CMOS Multi-threshold Transistors KS Sivasundar M International Journal of Scientific & Engineering Research 5 (5), 757-762, 2014 | 1 | 2014 |
| Small-Swing Cross-Coupled Inverters Based Low-Power Embedded Memory in Logic CMOS Technology S Manisankar, Y Chung International Journal of Applied Engineering Research 11 (4), 2749-2754, 2016 | | 2016 |
| A Gain Cell eDRAM in Logic CMOS Technology W Cheng, H Das, S Manisankar, Y Chung | | |
| A Gain Cell Array with Retention Increment Design for Bit-Area Efficient On-Chip Memory Applications S Manisankar, H Kim, Y Chung | | |
Taehoon KimKyungpook National UniversityVerified email at ee.knu.ac.kr
